DE69434049T2 - Keramisches Substrat und Verfahren zu dessen Herstellung - Google Patents

Keramisches Substrat und Verfahren zu dessen Herstellung Download PDF

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Publication number
DE69434049T2
DE69434049T2 DE69434049T DE69434049T DE69434049T2 DE 69434049 T2 DE69434049 T2 DE 69434049T2 DE 69434049 T DE69434049 T DE 69434049T DE 69434049 T DE69434049 T DE 69434049T DE 69434049 T2 DE69434049 T2 DE 69434049T2
Authority
DE
Germany
Prior art keywords
paste
forming
layer
substrate
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69434049T
Other languages
German (de)
English (en)
Other versions
DE69434049D1 (de
Inventor
Yoshifumi Neyagawa-shi Nakamura
Yoshihiro Higashiosaka-shi Bessho
Satoru Osaka-shi Yuhaku
Yasuhiko Nishinomiya-shi Hakotani
Minehiro Moriguchi-shi Itagaki
Kazuhiro Asahi-ku Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69434049D1 publication Critical patent/DE69434049D1/de
Application granted granted Critical
Publication of DE69434049T2 publication Critical patent/DE69434049T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/035—Paste overlayer, i.e. conductive paste or solder paste over conductive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49163—Manufacturing circuit on or in base with sintering of base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
DE69434049T 1993-02-02 1994-02-02 Keramisches Substrat und Verfahren zu dessen Herstellung Expired - Fee Related DE69434049T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1520393 1993-02-02
JP1520393 1993-02-02

Publications (2)

Publication Number Publication Date
DE69434049D1 DE69434049D1 (de) 2004-11-11
DE69434049T2 true DE69434049T2 (de) 2005-02-10

Family

ID=11882315

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69434049T Expired - Fee Related DE69434049T2 (de) 1993-02-02 1994-02-02 Keramisches Substrat und Verfahren zu dessen Herstellung

Country Status (5)

Country Link
US (2) US5547530A (enExample)
EP (1) EP0609861B1 (enExample)
KR (1) KR0179404B1 (enExample)
DE (1) DE69434049T2 (enExample)
TW (1) TW256826B (enExample)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143421A (en) * 1992-09-17 2000-11-07 Coorstek, Inc. Electronic components incorporating ceramic-metal composites
DE4400532C1 (de) * 1994-01-11 1995-03-23 Siemens Ag Verfahren zum Herstellen von Flüssigkontakten in Kontaktlöchern
JPH07221104A (ja) * 1994-01-28 1995-08-18 Fujitsu Ltd 半導体装置の製造方法及び半導体装置及び電極ピン形成用マスク及び電極ピン形成用マスクを用いた試験方法
US5539153A (en) * 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
US6033764A (en) * 1994-12-16 2000-03-07 Zecal Corp. Bumped substrate assembly
WO1996039298A1 (en) * 1995-06-06 1996-12-12 Sarnoff Corporation Method for the reduction of lateral shrinkage in multilayer circuit boards on a support
US6709749B1 (en) * 1995-06-06 2004-03-23 Lamina Ceramics, Inc. Method for the reduction of lateral shrinkage in multilayer circuit boards on a substrate
DE19541976A1 (de) * 1995-11-10 1997-05-15 Ego Elektro Blanc & Fischer Elektrische Schaltung
JP2751912B2 (ja) * 1996-03-28 1998-05-18 日本電気株式会社 半導体装置およびその製造方法
DE19634646A1 (de) 1996-08-27 1998-03-05 Pac Tech Gmbh Verfahren zur selektiven Belotung
JPH10107440A (ja) * 1996-09-30 1998-04-24 Sumitomo Kinzoku Electro Device:Kk セラミック基板及びその製造方法
JP3570599B2 (ja) * 1997-01-14 2004-09-29 株式会社村田製作所 圧電素子およびその製造方法
US6230963B1 (en) 1997-01-28 2001-05-15 Eric L. Hertz Method and apparatus using colored foils for placing conductive preforms
US6202918B1 (en) 1997-01-28 2001-03-20 Eric Hertz Method and apparatus for placing conductive preforms
US6056190A (en) * 1997-02-06 2000-05-02 Speedline Technologies, Inc. Solder ball placement apparatus
US6641030B1 (en) 1997-02-06 2003-11-04 Speedline Technologies, Inc. Method and apparatus for placing solder balls on a substrate
US6427903B1 (en) 1997-02-06 2002-08-06 Speedline Technologies, Inc. Solder ball placement apparatus
US6162661A (en) * 1997-05-30 2000-12-19 Tessera, Inc. Spacer plate solder ball placement fixture and methods therefor
JP3889856B2 (ja) * 1997-06-30 2007-03-07 松下電器産業株式会社 突起電極付きプリント配線基板の製造方法
US5904502A (en) * 1997-09-04 1999-05-18 International Business Machines Corporation Multiple 3-dimensional semiconductor device processing method and apparatus
US5924003A (en) * 1997-11-14 1999-07-13 Kinetrix, Inc. Method of manufacturing ball grid arrays for improved testability
US6117367A (en) * 1998-02-09 2000-09-12 International Business Machines Corporation Pastes for improved substrate dimensional control
US6300254B1 (en) * 1998-04-17 2001-10-09 Tessera, Inc. Methods of making compliant interfaces and microelectronic packages using same
US5923955A (en) * 1998-05-28 1999-07-13 Xerox Corporation Fine flip chip interconnection
JP4151136B2 (ja) 1998-06-15 2008-09-17 松下電器産業株式会社 基板および半導体装置とその製造方法
DE19842276A1 (de) * 1998-09-16 2000-03-30 Bosch Gmbh Robert Paste zum Verschweißen von Keramiken mit Metallen und Verfahren zur Herstellung einer Schweißverbindung
JP3771099B2 (ja) * 1999-01-27 2006-04-26 松下電器産業株式会社 グリーンシート及びその製造方法、多層配線基板の製造方法、両面配線基板の製造方法
US6376054B1 (en) * 1999-02-10 2002-04-23 International Business Machines Corporation Surface metallization structure for multiple chip test and burn-in
US6047637A (en) * 1999-06-17 2000-04-11 Fujitsu Limited Method of paste printing using stencil and masking layer
US6361735B1 (en) * 1999-09-01 2002-03-26 General Electric Company Composite ceramic article and method of making
KR100315751B1 (ko) * 1999-12-31 2001-12-12 송재인 저온 소성 세라믹 다층기판
WO2001058007A1 (en) * 2000-01-31 2001-08-09 Kinseki Limited Vessel for oscillation circuits using piezoelectric vibrator, method of producing the same, and oscillator
DE10035170B4 (de) * 2000-07-19 2005-11-24 Siemens Ag Keramikkörper mit Temperiervorrichtung, Verfahren zum Herstellen und Verwendung des Keramikkörpers
US7506438B1 (en) * 2000-11-14 2009-03-24 Freescale Semiconductor, Inc. Low profile integrated module interconnects and method of fabrication
US20040099441A1 (en) * 2001-04-24 2004-05-27 Akira Ichiryu Printed circuit board,its manufacturing method and csp manufacturing method
JP4034073B2 (ja) * 2001-05-11 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
KR20030050396A (ko) * 2001-12-18 2003-06-25 오리온전기 주식회사 저온 동시 소성 세라믹 모듈 제조 방법
KR20040051961A (ko) * 2002-12-13 2004-06-19 삼화전자공업 주식회사 태양전지용 기판 및 그 제조방법
DE112004000094A5 (de) * 2003-02-25 2008-04-03 Schott Ag Antimikrobiell wirkendes Borosilicatglas
US7378049B2 (en) * 2003-12-08 2008-05-27 Matsushita Electric Industrial Co., Ltd. Method for producing ceramic substrate and electronic component module using ceramic substrate
KR100853144B1 (ko) * 2004-09-03 2008-08-20 가부시키가이샤 무라타 세이사쿠쇼 칩형 전자부품을 탑재한 세라믹 기판 및 그 제조방법
WO2006035528A1 (ja) * 2004-09-29 2006-04-06 Murata Manufacturing Co., Ltd. スタックモジュール及びその製造方法
US20090139759A1 (en) * 2004-12-20 2009-06-04 Murata Manufacturing Co., Ltd. Laminated ceramic electronic component and manufacturing method therefor
WO2008004423A1 (en) * 2006-06-15 2008-01-10 Murata Manufacturing Co., Ltd. Wiring board having columnar conductor and method for manufacturing the wiring board
US7782629B2 (en) * 2007-02-26 2010-08-24 Flextronics Ap, Llc Embedding an electronic component between surfaces of a printed circuit board
JP4361572B2 (ja) * 2007-02-28 2009-11-11 株式会社新川 ボンディング装置及び方法
JP4337949B2 (ja) * 2007-09-06 2009-09-30 株式会社村田製作所 回路基板及び回路基板の製造方法
WO2009031588A1 (ja) * 2007-09-06 2009-03-12 Murata Manufacturing Co., Ltd. 回路基板、回路モジュール及び回路基板の製造方法
US8210424B2 (en) * 2010-09-16 2012-07-03 Hewlett-Packard Development Company, L.P. Soldering entities to a monolithic metallic sheet
WO2015048808A1 (en) * 2013-09-30 2015-04-02 Wolf Joseph Ambrose Silver thick film paste hermetically sealed by surface thin film multilayer
KR102019794B1 (ko) * 2017-06-29 2019-09-09 주식회사 디아이티 프로브 핀의 내구성 강화를 위한 스페이스 트랜스포머 및 그의 제조 방법
CN117652210A (zh) * 2021-07-05 2024-03-05 株式会社村田制作所 电路基板
WO2025005457A1 (ko) * 2023-06-29 2025-01-02 (주) 알엔투테크놀로지 세라믹 회로 기판, 그 제조방법, 및 이를 구비한 양면 냉각형 파워 모듈
WO2025005463A1 (ko) * 2023-06-29 2025-01-02 (주) 알엔투테크놀로지 세라믹 회로 기판, 그 제조방법, 및 이를 구비한 양면 냉각형 파워 모듈
WO2025005462A1 (ko) * 2023-06-29 2025-01-02 (주) 알엔투테크놀로지 세라믹 회로 기판, 그 제조방법, 및 이를 구비한 양면 냉각형 파워 모듈

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4461077A (en) * 1982-10-04 1984-07-24 General Electric Ceramics, Inc. Method for preparing ceramic articles having raised, selectively metallized electrical contact points
JPS61188942A (ja) * 1985-02-15 1986-08-22 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション はんだ接続体及びその形成方法
US5130067A (en) * 1986-05-02 1992-07-14 International Business Machines Corporation Method and means for co-sintering ceramic/metal mlc substrates
JPH02148789A (ja) * 1988-03-11 1990-06-07 Internatl Business Mach Corp <Ibm> 電子回路基板
JPH01293539A (ja) * 1988-05-23 1989-11-27 Fuji Xerox Co Ltd 半導体装置におけるバンプの形成方法
JPH0292936A (ja) * 1988-09-30 1990-04-03 Kuraray Co Ltd 透明樹脂または透明成形品の製造方法
JP2680443B2 (ja) * 1989-09-27 1997-11-19 株式会社東芝 セラミック配線基板およびその製造方法
US5085720A (en) * 1990-01-18 1992-02-04 E. I. Du Pont De Nemours And Company Method for reducing shrinkage during firing of green ceramic bodies
WO1991011307A1 (fr) * 1990-01-25 1991-08-08 Dai Nippon Insatsu Kabushiki Kaisha Procede et matiere pour former des films epais textures
JP2590450B2 (ja) * 1990-02-05 1997-03-12 株式会社村田製作所 バンプ電極の形成方法
JP3154713B2 (ja) * 1990-03-16 2001-04-09 株式会社リコー 異方性導電膜およびその製造方法
EP0516866A1 (en) * 1991-05-03 1992-12-09 International Business Machines Corporation Modular multilayer interwiring structure
JP3203731B2 (ja) * 1992-02-05 2001-08-27 松下電器産業株式会社 半導体素子基板および実装方法、柱状端子付き基板およびその製造方法
JP2601128B2 (ja) * 1992-05-06 1997-04-16 松下電器産業株式会社 回路形成用基板の製造方法および回路形成用基板
WO1994007348A1 (en) * 1992-09-24 1994-03-31 Hughes Aircraft Company Dielectric vias within multilayer 3-dimensional structures/substrates

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US5525402A (en) 1996-06-11
DE69434049D1 (de) 2004-11-11
EP0609861A3 (en) 1995-01-04
US5547530A (en) 1996-08-20
KR0179404B1 (ko) 1999-05-15
TW256826B (enExample) 1995-09-11
EP0609861B1 (en) 2004-10-06
EP0609861A2 (en) 1994-08-10

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