DE3485930T2 - Mehrschichtiges keramisches substrat und verfahren zum herstellen desselben. - Google Patents

Mehrschichtiges keramisches substrat und verfahren zum herstellen desselben.

Info

Publication number
DE3485930T2
DE3485930T2 DE8484107705T DE3485930T DE3485930T2 DE 3485930 T2 DE3485930 T2 DE 3485930T2 DE 8484107705 T DE8484107705 T DE 8484107705T DE 3485930 T DE3485930 T DE 3485930T DE 3485930 T2 DE3485930 T2 DE 3485930T2
Authority
DE
Germany
Prior art keywords
producing
same
ceramic substrate
multilayer ceramic
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484107705T
Other languages
English (en)
Other versions
DE3485930D1 (de
Inventor
Yutaka Watanabe
Fumiyuki Kobayashi
Satoru Ogihara
Yoshiyuki Ohzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE3485930D1 publication Critical patent/DE3485930D1/de
Application granted granted Critical
Publication of DE3485930T2 publication Critical patent/DE3485930T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/4807—Ceramic parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676—Single layer compositions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Compositions Of Oxide Ceramics (AREA)
  • Laminated Bodies (AREA)
DE8484107705T 1983-07-04 1984-07-03 Mehrschichtiges keramisches substrat und verfahren zum herstellen desselben. Expired - Fee Related DE3485930T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58120359A JPS6014494A (ja) 1983-07-04 1983-07-04 セラミツク多層配線基板およびその製造方法

Publications (2)

Publication Number Publication Date
DE3485930D1 DE3485930D1 (de) 1992-10-29
DE3485930T2 true DE3485930T2 (de) 1993-05-06

Family

ID=14784248

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484107705T Expired - Fee Related DE3485930T2 (de) 1983-07-04 1984-07-03 Mehrschichtiges keramisches substrat und verfahren zum herstellen desselben.

Country Status (4)

Country Link
US (1) US4624896A (de)
EP (1) EP0131242B1 (de)
JP (1) JPS6014494A (de)
DE (1) DE3485930T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61266350A (ja) * 1985-05-21 1986-11-26 株式会社日立製作所 配線回路用セラミック基板
US4729010A (en) * 1985-08-05 1988-03-01 Hitachi, Ltd. Integrated circuit package with low-thermal expansion lead pieces
JPS6273799A (ja) * 1985-09-27 1987-04-04 日本電気株式会社 多層セラミツク配線基板
JPS62148365A (ja) * 1985-12-20 1987-07-02 富士通株式会社 低誘電性セラミツク板
JPH0632355B2 (ja) * 1986-01-27 1994-04-27 株式会社日立製作所 セラミツク配線基板とその製造方法
US4753694A (en) * 1986-05-02 1988-06-28 International Business Machines Corporation Process for forming multilayered ceramic substrate having solid metal conductors
JPS63107095A (ja) * 1986-10-23 1988-05-12 富士通株式会社 多層セラミツク回路基板
US4740414A (en) * 1986-11-17 1988-04-26 Rockwell International Corporation Ceramic/organic multilayer interconnection board
US4835039A (en) * 1986-11-26 1989-05-30 Ceramics Process Systems Corporation Tungsten paste for co-sintering with pure alumina and method for producing same
DE3705440A1 (de) * 1987-02-20 1988-09-01 Man Technologie Gmbh Waermeisolierung fuer hohe temperaturen
JPS63245952A (ja) * 1987-04-01 1988-10-13 Hitachi Ltd マルチチップモジュ−ル構造体
US4781970A (en) * 1987-07-15 1988-11-01 International Business Machines Corporation Strengthening a ceramic by post sinter coating with a compressive surface layer
JPH01169989A (ja) * 1987-12-24 1989-07-05 Ngk Insulators Ltd セラミックグリーンシート
JPH0611018B2 (ja) * 1988-01-07 1994-02-09 株式会社村田製作所 セラミック生シートの積層方法
US4880684A (en) * 1988-03-11 1989-11-14 International Business Machines Corporation Sealing and stress relief layers and use thereof
JP2551224B2 (ja) * 1990-10-17 1996-11-06 日本電気株式会社 多層配線基板および多層配線基板の製造方法
US5158912A (en) * 1991-04-09 1992-10-27 Digital Equipment Corporation Integral heatsink semiconductor package
EP0575813B1 (de) * 1992-06-08 1996-12-27 NEC Corporation Glaskeramisches Mehrschichtsubstrat und Verfahren zur seiner Herstellung
JP2960276B2 (ja) * 1992-07-30 1999-10-06 株式会社東芝 多層配線基板、この基板を用いた半導体装置及び多層配線基板の製造方法
US5456778A (en) * 1992-08-21 1995-10-10 Sumitomo Metal Ceramics Inc. Method of fabricating ceramic circuit substrate
JPH08181443A (ja) * 1994-12-21 1996-07-12 Murata Mfg Co Ltd セラミック多層基板およびその製造方法
JP3451868B2 (ja) * 1997-01-17 2003-09-29 株式会社デンソー セラミック積層基板の製造方法
US6080468A (en) * 1997-02-28 2000-06-27 Taiyo Yuden Co., Ltd. Laminated composite electronic device and a manufacturing method thereof
JPH11160356A (ja) * 1997-11-25 1999-06-18 Matsushita Electric Ind Co Ltd ウェハ一括型測定検査用プローブカードおよびセラミック多層配線基板ならびにそれらの製造方法
JP3601679B2 (ja) * 1999-07-27 2004-12-15 株式会社村田製作所 複合積層体の製造方法
JP3882500B2 (ja) * 2000-03-02 2007-02-14 株式会社村田製作所 厚膜絶縁組成物およびそれを用いたセラミック電子部品、ならびに電子装置
DE10227658B4 (de) * 2002-06-20 2012-03-08 Curamik Electronics Gmbh Metall-Keramik-Substrat für elektrische Schaltkreise -oder Module, Verfahren zum Herstellen eines solchen Substrates sowie Modul mit einem solchen Substrat
US20040226319A1 (en) * 2003-05-15 2004-11-18 Macchesney John Burnette Chemical powder deposition method for the manufacture of optical fiber preforms and optical fibers
US6815813B1 (en) * 2003-07-01 2004-11-09 International Business Machines Corporation Self-contained heat sink and a method for fabricating same
US9583426B2 (en) 2014-11-05 2017-02-28 Invensas Corporation Multi-layer substrates suitable for interconnection between circuit modules
US10283492B2 (en) 2015-06-23 2019-05-07 Invensas Corporation Laminated interposers and packages with embedded trace interconnects
US9852994B2 (en) 2015-12-14 2017-12-26 Invensas Corporation Embedded vialess bridges

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4387131A (en) * 1971-06-30 1983-06-07 International Business Machines Corporation Ceramic dielectrics
JPS5548700B2 (de) * 1973-01-30 1980-12-08
US4032350A (en) * 1973-03-12 1977-06-28 Owens-Illinois, Inc. Printing paste vehicle, gold dispensing paste and method of using the paste in the manufacture of microelectronic circuitry components
DE2332822B2 (de) * 1973-06-28 1978-04-27 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum Herstellen von diffundierten, kontaktierten und oberflächenpassivierten Halbleiterbauelementen aus Halbleiterscheiben aus Silizium
US4137355A (en) * 1976-12-09 1979-01-30 Honeywell Inc. Ceramic coated with molten silicon
US4094704A (en) * 1977-05-11 1978-06-13 Milnes Arthur G Dual electrically insulated solar cells
US4161746A (en) * 1978-03-28 1979-07-17 Westinghouse Electric Corp. Glass sealed diode
CA1161238A (en) * 1979-03-02 1984-01-31 Robert Smith-Johannsen Inorganic composite structures
JPS55133597A (en) * 1979-04-06 1980-10-17 Hitachi Ltd Multilayer circuit board
JPS55139709A (en) * 1979-04-18 1980-10-31 Fujitsu Ltd Method of fabricating mullite substrate
JPS57184296A (en) * 1981-05-09 1982-11-12 Hitachi Ltd Ceramic circuit board

Also Published As

Publication number Publication date
US4624896A (en) 1986-11-25
DE3485930D1 (de) 1992-10-29
EP0131242A2 (de) 1985-01-16
JPS6014494A (ja) 1985-01-25
EP0131242A3 (en) 1986-12-30
EP0131242B1 (de) 1992-09-23

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee