DE69426087T2 - Halbleiterspeichervorrichtung mit Testschaltung - Google Patents

Halbleiterspeichervorrichtung mit Testschaltung

Info

Publication number
DE69426087T2
DE69426087T2 DE69426087T DE69426087T DE69426087T2 DE 69426087 T2 DE69426087 T2 DE 69426087T2 DE 69426087 T DE69426087 T DE 69426087T DE 69426087 T DE69426087 T DE 69426087T DE 69426087 T2 DE69426087 T2 DE 69426087T2
Authority
DE
Germany
Prior art keywords
transistors
node
data signal
series
driven
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69426087T
Other languages
English (en)
Other versions
DE69426087D1 (de
Inventor
Yoshinori Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69426087D1 publication Critical patent/DE69426087D1/de
Publication of DE69426087T2 publication Critical patent/DE69426087T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Static Random-Access Memory (AREA)
DE69426087T 1993-01-25 1994-01-24 Halbleiterspeichervorrichtung mit Testschaltung Expired - Fee Related DE69426087T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5009632A JP2601120B2 (ja) 1993-01-25 1993-01-25 並列テスト回路

Publications (2)

Publication Number Publication Date
DE69426087D1 DE69426087D1 (de) 2000-11-16
DE69426087T2 true DE69426087T2 (de) 2001-05-17

Family

ID=11725620

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69426087T Expired - Fee Related DE69426087T2 (de) 1993-01-25 1994-01-24 Halbleiterspeichervorrichtung mit Testschaltung

Country Status (5)

Country Link
US (1) US5444661A (de)
EP (1) EP0617429B1 (de)
JP (1) JP2601120B2 (de)
KR (1) KR0132653B1 (de)
DE (1) DE69426087T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3409527B2 (ja) * 1995-08-17 2003-05-26 富士通株式会社 半導体記憶装置
KR100212420B1 (ko) * 1995-09-25 1999-08-02 김영환 테스트회로를 내장한 캐쉬 스태틱램
JPH09147598A (ja) * 1995-11-28 1997-06-06 Mitsubishi Electric Corp 半導体記憶装置およびアドレス変化検出回路
CN1121696C (zh) * 1997-08-04 2003-09-17 三菱电机株式会社 能够实现稳定的检验方式操作的半导体存储器
JP3716080B2 (ja) * 1997-08-28 2005-11-16 エルピーダメモリ株式会社 半導体記憶装置の出力回路
DE19742597A1 (de) * 1997-09-26 1999-04-08 Siemens Ag Digitaler Speicher und Betriebsverfahren für einen digitalen Speicher
KR100576482B1 (ko) * 1998-12-24 2006-09-27 주식회사 하이닉스반도체 멀티비트 데이터 테스트 장치
KR200306735Y1 (ko) * 2002-12-03 2003-03-11 김명국 좌욕전용 템포

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226589A (ja) * 1989-02-27 1990-09-10 Nec Corp 半導体記憶装置
JPH04212799A (ja) * 1990-01-31 1992-08-04 Nec Ic Microcomput Syst Ltd テスト回路内蔵半導体メモリ
JPH04356799A (ja) * 1990-08-29 1992-12-10 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
JP2601120B2 (ja) 1997-04-16
KR940018985A (ko) 1994-08-19
KR0132653B1 (ko) 1998-04-16
EP0617429A3 (de) 1997-07-23
US5444661A (en) 1995-08-22
JPH06223596A (ja) 1994-08-12
EP0617429B1 (de) 2000-10-11
DE69426087D1 (de) 2000-11-16
EP0617429A2 (de) 1994-09-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee