DE69322581D1 - Halbleiterspeichergerät mit einer Adressenübergangsdetektorschaltung zur schnellen Inbetriebnahme eines redundanten Dekoders - Google Patents

Halbleiterspeichergerät mit einer Adressenübergangsdetektorschaltung zur schnellen Inbetriebnahme eines redundanten Dekoders

Info

Publication number
DE69322581D1
DE69322581D1 DE69322581T DE69322581T DE69322581D1 DE 69322581 D1 DE69322581 D1 DE 69322581D1 DE 69322581 T DE69322581 T DE 69322581T DE 69322581 T DE69322581 T DE 69322581T DE 69322581 D1 DE69322581 D1 DE 69322581D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
detector circuit
address transition
transition detector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69322581T
Other languages
English (en)
Other versions
DE69322581T2 (de
Inventor
Munehiro Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69322581D1 publication Critical patent/DE69322581D1/de
Publication of DE69322581T2 publication Critical patent/DE69322581T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69322581T 1992-09-24 1993-09-23 Halbleiterspeichergerät mit einer Adressenübergangsdetektorschaltung zur schnellen Inbetriebnahme eines redundanten Dekoders Expired - Lifetime DE69322581T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4255058A JP2734315B2 (ja) 1992-09-24 1992-09-24 半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE69322581D1 true DE69322581D1 (de) 1999-01-28
DE69322581T2 DE69322581T2 (de) 1999-07-01

Family

ID=17273564

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69322581T Expired - Lifetime DE69322581T2 (de) 1992-09-24 1993-09-23 Halbleiterspeichergerät mit einer Adressenübergangsdetektorschaltung zur schnellen Inbetriebnahme eines redundanten Dekoders

Country Status (5)

Country Link
US (1) US5414659A (de)
EP (1) EP0591776B1 (de)
JP (1) JP2734315B2 (de)
KR (1) KR950014098B1 (de)
DE (1) DE69322581T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481500A (en) * 1994-07-22 1996-01-02 International Business Machines Corporation Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories
FR2724483B1 (fr) * 1994-09-12 1996-12-27 Sgs Thomson Microelectronics Procede de decodage d'adresse dans une memoire en circuit integre et circuit memoire mettant en oeuvre le procede
JP3425811B2 (ja) * 1994-09-28 2003-07-14 Necエレクトロニクス株式会社 半導体メモリ
JP2630274B2 (ja) * 1994-09-28 1997-07-16 日本電気株式会社 半導体記憶装置
KR0177740B1 (ko) * 1994-11-17 1999-04-15 김광호 반도체 메모리 장치의 리던던시 회로 및 그 방법
US5713005A (en) * 1995-02-10 1998-01-27 Townsend And Townsend And Crew Llp Method and apparatus for pipelining data in an integrated circuit
JPH09153288A (ja) * 1995-11-30 1997-06-10 Mitsubishi Electric Corp 半導体記憶装置
US5757718A (en) * 1996-02-28 1998-05-26 Nec Corporation Semiconductor memory device having address transition detection circuit for controlling sense and latch operations
DE69616747T2 (de) * 1996-03-29 2002-08-08 Stmicroelectronics S.R.L., Agrate Brianza Redundanzverwaltungsverfahren und -architektur, insbesondere für nicht-flüchtige Speicher
US5691946A (en) * 1996-12-03 1997-11-25 International Business Machines Corporation Row redundancy block architecture
IT1294367B1 (it) * 1997-08-29 1999-03-24 Sgs Thomson Microelectronics Circuiteria atd immune nei confronti di impulsi spuri
US5963489A (en) * 1998-03-24 1999-10-05 International Business Machines Corporation Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device
KR100549943B1 (ko) * 1999-09-08 2006-02-07 삼성전자주식회사 반도체 메모리 장치의 리던던시 디코더
KR100732746B1 (ko) * 2001-06-29 2007-06-27 주식회사 하이닉스반도체 동기 메모리 소자의 칼럼 리던던시 프리차지 회로
JP2003100094A (ja) * 2001-09-27 2003-04-04 Mitsubishi Electric Corp 半導体記憶装置
US6728123B2 (en) 2002-04-15 2004-04-27 International Business Machines Corporation Redundant array architecture for word replacement in CAM
DE10239857A1 (de) * 2002-08-29 2004-03-18 Infineon Technologies Ag Verfahren zum Ansteuern von einmalig betreibbaren Trennelementen
KR100598114B1 (ko) * 2005-01-25 2006-07-10 삼성전자주식회사 페이지 모드 동작을 수행하는 반도체 메모리 장치
US7268589B2 (en) * 2005-12-16 2007-09-11 Actel Corporation Address transition detector for fast flash memory device
JP2010245988A (ja) * 2009-04-09 2010-10-28 Yazaki Corp 通信アドレス検出装置、制御回路内蔵コネクタ、及び、通信アドレス検出方法
JP5529661B2 (ja) * 2010-07-23 2014-06-25 ラピスセミコンダクタ株式会社 半導体メモリ
IT1404183B1 (it) 2011-02-28 2013-11-15 St Microelectronics Srl Dispositivo di decodifica di indirizzo
US10044342B2 (en) 2016-06-09 2018-08-07 Qualcomm Incorporated Delay line for one shot pre-emphasis

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6337899A (ja) * 1986-07-30 1988-02-18 Mitsubishi Electric Corp 半導体記憶装置
US4689494A (en) * 1986-09-18 1987-08-25 Advanced Micro Devices, Inc. Redundancy enable/disable circuit
JPH07105157B2 (ja) * 1987-09-10 1995-11-13 日本電気株式会社 冗長メモリセル使用判定回路
ATE87753T1 (de) * 1988-02-10 1993-04-15 Siemens Ag Redundanzdekoder eines integrierten halbleiterspeichers.
US5289417A (en) * 1989-05-09 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with redundancy circuit
KR930000821B1 (ko) * 1990-02-24 1993-02-05 현대전자산업 주식회사 메모리 소자의 저소비 전력 리던던시(Redundancy)회로
JP2600435B2 (ja) * 1990-05-08 1997-04-16 松下電器産業株式会社 冗長救済回路
EP0469571B1 (de) * 1990-07-31 1997-11-12 Texas Instruments Incorporated Redundante Halbleiterspeicheranordnung
JP2629475B2 (ja) * 1991-04-04 1997-07-09 松下電器産業株式会社 半導体集積回路
JP2888034B2 (ja) * 1991-06-27 1999-05-10 日本電気株式会社 半導体メモリ装置

Also Published As

Publication number Publication date
EP0591776A2 (de) 1994-04-13
JP2734315B2 (ja) 1998-03-30
EP0591776B1 (de) 1998-12-16
DE69322581T2 (de) 1999-07-01
JPH06111597A (ja) 1994-04-22
KR950014098B1 (ko) 1995-11-21
US5414659A (en) 1995-05-09
EP0591776A3 (de) 1994-11-02
KR940007893A (ko) 1994-04-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP