DE69421753D1 - Halbleiter Speicheranordnung mit einem Prüfmodus zur Ausführung einer automatischen Auffrischungsfunktion - Google Patents

Halbleiter Speicheranordnung mit einem Prüfmodus zur Ausführung einer automatischen Auffrischungsfunktion

Info

Publication number
DE69421753D1
DE69421753D1 DE69421753T DE69421753T DE69421753D1 DE 69421753 D1 DE69421753 D1 DE 69421753D1 DE 69421753 T DE69421753 T DE 69421753T DE 69421753 T DE69421753 T DE 69421753T DE 69421753 D1 DE69421753 D1 DE 69421753D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
test mode
refresh function
automatic refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69421753T
Other languages
English (en)
Other versions
DE69421753T2 (de
Inventor
Shinya Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69421753D1 publication Critical patent/DE69421753D1/de
Application granted granted Critical
Publication of DE69421753T2 publication Critical patent/DE69421753T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69421753T 1993-06-15 1994-06-15 Halbleiter Speicheranordnung mit einem Prüfmodus zur Ausführung einer automatischen Auffrischungsfunktion Expired - Fee Related DE69421753T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5143354A JP3059024B2 (ja) 1993-06-15 1993-06-15 半導体記憶回路

Publications (2)

Publication Number Publication Date
DE69421753D1 true DE69421753D1 (de) 1999-12-30
DE69421753T2 DE69421753T2 (de) 2000-05-31

Family

ID=15336842

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69421753T Expired - Fee Related DE69421753T2 (de) 1993-06-15 1994-06-15 Halbleiter Speicheranordnung mit einem Prüfmodus zur Ausführung einer automatischen Auffrischungsfunktion

Country Status (5)

Country Link
US (1) US5502677A (de)
EP (1) EP0630026B1 (de)
JP (1) JP3059024B2 (de)
KR (1) KR100227395B1 (de)
DE (1) DE69421753T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0142795B1 (ko) * 1994-12-01 1998-08-17 문정환 디램 리프레쉬 회로
JP3260583B2 (ja) * 1995-04-04 2002-02-25 株式会社東芝 ダイナミック型半導体メモリおよびそのテスト方法
JP3664777B2 (ja) * 1995-08-18 2005-06-29 株式会社ルネサステクノロジ 半導体記憶装置
KR100372245B1 (ko) * 1995-08-24 2004-02-25 삼성전자주식회사 워드라인순차제어반도체메모리장치
JP2760333B2 (ja) * 1995-11-17 1998-05-28 日本電気株式会社 半導体装置
KR100206600B1 (ko) * 1996-06-03 1999-07-01 김영환 싱크로노스 디램의 리프레쉬 카운터 테스트 모드방법 및 그 장치
DE19711097C2 (de) * 1997-03-17 2000-04-06 Siemens Ag Integrierte Schaltung mit einem Speicher und einer Prüfschaltung
US6161204A (en) * 1998-02-17 2000-12-12 Micron Technology, Inc. Method and apparatus for testing SRAM memory cells
JPH11345486A (ja) * 1998-06-01 1999-12-14 Mitsubishi Electric Corp セルフ・リフレッシュ制御回路を備えたｄｒａｍおよびシステムｌｓｉ
US6694463B2 (en) * 2001-01-16 2004-02-17 Atmel Corporation Input/output continuity test mode circuit
US10426578B2 (en) 2006-10-16 2019-10-01 Natural Dental Implants, Ag Customized dental prosthesis for periodontal or osseointegration and related systems
US8602780B2 (en) 2006-10-16 2013-12-10 Natural Dental Implants, Ag Customized dental prosthesis for periodontal or osseointegration and related systems and methods
KR101752154B1 (ko) * 2010-11-02 2017-06-30 삼성전자주식회사 로우 어드레스 제어 회로, 이를 포함하는 반도체 메모리 장치 및 로우 어드레스 제어 방법
KR102194791B1 (ko) * 2013-08-09 2020-12-28 에스케이하이닉스 주식회사 메모리, 이를 포함하는 메모리 시스템 및 메모리의 동작방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63148493A (ja) * 1986-12-11 1988-06-21 Nec Ic Microcomput Syst Ltd 擬似スタチツクメモリ
JPH02131010A (ja) * 1988-11-10 1990-05-18 Fujitsu Ltd アドレス変化検出回路
JP2928263B2 (ja) * 1989-03-20 1999-08-03 株式会社日立製作所 半導体装置
KR940003408B1 (ko) * 1991-07-31 1994-04-21 삼성전자 주식회사 어드레스 천이 검출회로(atd)를 내장한 반도체 메모리 장치
JPH05166396A (ja) * 1991-12-12 1993-07-02 Mitsubishi Electric Corp 半導体メモリ装置
JP2977385B2 (ja) * 1992-08-31 1999-11-15 株式会社東芝 ダイナミックメモリ装置

Also Published As

Publication number Publication date
KR100227395B1 (ko) 1999-11-01
KR950001766A (ko) 1995-01-03
EP0630026A2 (de) 1994-12-21
US5502677A (en) 1996-03-26
JPH0714400A (ja) 1995-01-17
DE69421753T2 (de) 2000-05-31
EP0630026B1 (de) 1999-11-24
EP0630026A3 (de) 1995-08-30
JP3059024B2 (ja) 2000-07-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee