DE69130589D1 - Halbleiterspeicheranordnung mit einer Treiberschaltung zur zweifachen Wortleitungsspannungserhöhung - Google Patents

Halbleiterspeicheranordnung mit einer Treiberschaltung zur zweifachen Wortleitungsspannungserhöhung

Info

Publication number
DE69130589D1
DE69130589D1 DE69130589T DE69130589T DE69130589D1 DE 69130589 D1 DE69130589 D1 DE 69130589D1 DE 69130589 T DE69130589 T DE 69130589T DE 69130589 T DE69130589 T DE 69130589T DE 69130589 D1 DE69130589 D1 DE 69130589D1
Authority
DE
Germany
Prior art keywords
twice
word line
semiconductor memory
driver circuit
line voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69130589T
Other languages
English (en)
Other versions
DE69130589T2 (de
Inventor
Yasukazu Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69130589D1 publication Critical patent/DE69130589D1/de
Application granted granted Critical
Publication of DE69130589T2 publication Critical patent/DE69130589T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
DE69130589T 1990-06-08 1991-06-07 Halbleiterspeicheranordnung mit einer Treiberschaltung zur zweifachen Wortleitungsspannungserhöhung Expired - Lifetime DE69130589T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2151287A JPH0442494A (ja) 1990-06-08 1990-06-08 Ｍｏｓダイナミックｒａｍ

Publications (2)

Publication Number Publication Date
DE69130589D1 true DE69130589D1 (de) 1999-01-21
DE69130589T2 DE69130589T2 (de) 1999-07-15

Family

ID=15515386

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130589T Expired - Lifetime DE69130589T2 (de) 1990-06-08 1991-06-07 Halbleiterspeicheranordnung mit einer Treiberschaltung zur zweifachen Wortleitungsspannungserhöhung

Country Status (5)

Country Link
US (1) US5287325A (de)
EP (1) EP0460694B1 (de)
JP (1) JPH0442494A (de)
KR (1) KR950009230B1 (de)
DE (1) DE69130589T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2739802B2 (ja) * 1992-12-01 1998-04-15 日本電気株式会社 ダイナミックｒａｍ装置
KR960011206B1 (ko) * 1993-11-09 1996-08-21 삼성전자 주식회사 반도체메모리장치의 워드라인구동회로
JP2895378B2 (ja) * 1993-12-28 1999-05-24 株式会社テノックス 緩斜面の急勾配化工法
US5724286A (en) * 1994-12-14 1998-03-03 Mosaid Technologies Incorporated Flexible DRAM array
KR0158485B1 (ko) * 1995-03-31 1999-02-01 김광호 본딩옵션용 워드라인전압 승압회로
JPH10228773A (ja) * 1997-02-14 1998-08-25 Hitachi Ltd ダイナミック型ｒａｍ
US6573548B2 (en) 1998-08-14 2003-06-03 Monolithic System Technology, Inc. DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same
US6147914A (en) * 1998-08-14 2000-11-14 Monolithic System Technology, Inc. On-chip word line voltage generation for DRAM embedded in logic process
US6509595B1 (en) * 1999-06-14 2003-01-21 Monolithic System Technology, Inc. DRAM cell fabricated using a modified logic process and method for operating same
US6468855B2 (en) 1998-08-14 2002-10-22 Monolithic System Technology, Inc. Reduced topography DRAM cell fabricated using a modified logic process and method for operating same
JP3654567B2 (ja) 1999-05-21 2005-06-02 本田技研工業株式会社 エンジン発電機
JP3856424B2 (ja) * 2000-12-25 2006-12-13 株式会社東芝 半導体記憶装置
KR20030070448A (ko) * 2002-02-25 2003-08-30 (주) 미건티알아이 초음파식 벼 활성화 조절기 및 그 조절방법
US6721210B1 (en) * 2002-08-30 2004-04-13 Nanoamp Solutions, Inc. Voltage boosting circuit for a low power semiconductor memory
US7323379B2 (en) 2005-02-03 2008-01-29 Mosys, Inc. Fabrication process for increased capacitance in an embedded DRAM memory
US7525853B2 (en) * 2005-08-12 2009-04-28 Spansion Llc Semiconductor device and method for boosting word line
JP2007220234A (ja) * 2006-02-17 2007-08-30 Matsushita Electric Ind Co Ltd 半導体記憶装置
US8331132B2 (en) * 2010-08-03 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Adaptive write bit line and word line adjusting mechanism for memory
US8526266B2 (en) * 2011-01-21 2013-09-03 Qualcomm Incorporated Row-decoder circuit and method with dual power systems
JP2013004136A (ja) 2011-06-15 2013-01-07 Elpida Memory Inc 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5718080A (en) * 1980-07-07 1982-01-29 Mitsubishi Electric Corp Readout and rewrite-in method for dynamic mos semiconductor memory
US4503522A (en) * 1981-03-17 1985-03-05 Hitachi, Ltd. Dynamic type semiconductor monolithic memory
US4649523A (en) * 1985-02-08 1987-03-10 At&T Bell Laboratories Semiconductor memory with boosted word line
JPS6437797A (en) * 1987-08-03 1989-02-08 Oki Electric Ind Co Ltd Eprom device
US4896297A (en) * 1987-10-23 1990-01-23 Mitsubishi Denki Kabushiki Kaisha Circuit for generating a boosted signal for a word line
JPH01162296A (ja) * 1987-12-19 1989-06-26 Sony Corp Ｄｒａｍ
JPH02247892A (ja) * 1989-03-20 1990-10-03 Fujitsu Ltd ダイナミックランダムアクセスメモリ

Also Published As

Publication number Publication date
EP0460694B1 (de) 1998-12-09
US5287325A (en) 1994-02-15
KR920001529A (ko) 1992-01-30
KR950009230B1 (ko) 1995-08-18
EP0460694A2 (de) 1991-12-11
JPH0442494A (ja) 1992-02-13
DE69130589T2 (de) 1999-07-15
EP0460694A3 (en) 1993-03-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP