DE69330505D1 - Halbleiterspeichergerät mit Redundanz - Google Patents

Halbleiterspeichergerät mit Redundanz

Info

Publication number
DE69330505D1
DE69330505D1 DE69330505T DE69330505T DE69330505D1 DE 69330505 D1 DE69330505 D1 DE 69330505D1 DE 69330505 T DE69330505 T DE 69330505T DE 69330505 T DE69330505 T DE 69330505T DE 69330505 D1 DE69330505 D1 DE 69330505D1
Authority
DE
Germany
Prior art keywords
redundancy
storage device
semiconductor storage
semiconductor
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69330505T
Other languages
English (en)
Other versions
DE69330505T2 (de
Inventor
Toshimasa Namekawa
Yoshio Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69330505D1 publication Critical patent/DE69330505D1/de
Application granted granted Critical
Publication of DE69330505T2 publication Critical patent/DE69330505T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
DE69330505T 1992-03-23 1993-03-23 Halbleiterspeichergerät mit Redundanz Expired - Fee Related DE69330505T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4064979A JP2567180B2 (ja) 1992-03-23 1992-03-23 半導体メモリ

Publications (2)

Publication Number Publication Date
DE69330505D1 true DE69330505D1 (de) 2001-09-06
DE69330505T2 DE69330505T2 (de) 2002-04-11

Family

ID=13273684

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69330505T Expired - Fee Related DE69330505T2 (de) 1992-03-23 1993-03-23 Halbleiterspeichergerät mit Redundanz

Country Status (5)

Country Link
US (1) US5357470A (de)
EP (1) EP0562548B1 (de)
JP (1) JP2567180B2 (de)
KR (1) KR960005899B1 (de)
DE (1) DE69330505T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2856645B2 (ja) * 1993-09-13 1999-02-10 株式会社東芝 半導体記憶装置
JPH07282597A (ja) * 1994-04-12 1995-10-27 Mitsubishi Electric Corp 半導体記憶装置
US5517138A (en) * 1994-09-30 1996-05-14 Intel Corporation Dual row selection using multiplexed tri-level decoder
WO1996015536A1 (en) * 1994-11-09 1996-05-23 Philips Electronics N.V. A method of testing a memory address decoder and a fault-tolerant memory address decoder
JPH08227597A (ja) * 1995-02-21 1996-09-03 Mitsubishi Electric Corp 半導体記憶装置
KR0145222B1 (ko) * 1995-05-20 1998-08-17 김광호 반도체 메모리장치의 메모리 셀 테스트 제어회로 및 방법
KR100195274B1 (ko) * 1995-12-28 1999-06-15 윤종용 리던던시 퓨즈 상자 및 그 배치 방법
KR100480566B1 (ko) * 1997-10-27 2005-09-30 삼성전자주식회사 반도체메모리장치의리던던시메모리셀테스트신호발생기
KR100526531B1 (ko) * 1998-12-30 2005-12-21 삼성전자주식회사 메모리장치의 어드레스 디코딩회로
KR20030000766A (ko) * 2001-06-27 2003-01-06 삼성전자 주식회사 반도체 메모리의 리던던시 회로
JP4012474B2 (ja) 2003-02-18 2007-11-21 富士通株式会社 シフト冗長回路、シフト冗長回路の制御方法及び半導体記憶装置
JP2008021390A (ja) * 2006-07-14 2008-01-31 Toshiba Corp 半導体記憶装置
KR100834443B1 (ko) 2007-02-27 2008-06-04 삼성전자주식회사 비디오 코덱을 위한 메모리 구조 및 메모리 액세스 방법
KR100936809B1 (ko) * 2008-01-18 2010-01-14 주식회사 하이닉스반도체 결함 단위셀의 구제를 위한 리던던시 회로를 포함한 반도체메모리 장치
US9111624B2 (en) 2013-03-22 2015-08-18 Katsuyuki Fujita Semiconductor memory device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0754639B2 (ja) * 1985-08-17 1995-06-07 三洋電機株式会社 半導体メモリ
JPH01184796A (ja) * 1988-01-19 1989-07-24 Nec Corp 半導体メモリ装置
KR920010347B1 (ko) * 1989-12-30 1992-11-27 삼성전자주식회사 분할된 워드라인을 가지는 메모리장치의 리던던시 구조
JP2629463B2 (ja) * 1991-01-25 1997-07-09 日本電気株式会社 半導体記憶回路
JP2730375B2 (ja) * 1992-01-31 1998-03-25 日本電気株式会社 半導体メモリ

Also Published As

Publication number Publication date
EP0562548A3 (de) 1998-01-14
JP2567180B2 (ja) 1996-12-25
KR930020477A (ko) 1993-10-19
EP0562548A2 (de) 1993-09-29
JPH0628890A (ja) 1994-02-04
DE69330505T2 (de) 2002-04-11
US5357470A (en) 1994-10-18
KR960005899B1 (ko) 1996-05-03
EP0562548B1 (de) 2001-08-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee