DE3855337D1 - Halbleiterspeichergerät mit verbessertem Redundanzschema - Google Patents

Halbleiterspeichergerät mit verbessertem Redundanzschema

Info

Publication number
DE3855337D1
DE3855337D1 DE3855337T DE3855337T DE3855337D1 DE 3855337 D1 DE3855337 D1 DE 3855337D1 DE 3855337 T DE3855337 T DE 3855337T DE 3855337 T DE3855337 T DE 3855337T DE 3855337 D1 DE3855337 D1 DE 3855337D1
Authority
DE
Germany
Prior art keywords
storage device
semiconductor storage
redundancy scheme
improved redundancy
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855337T
Other languages
English (en)
Other versions
DE3855337T2 (de
Inventor
Kenji Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3855337D1 publication Critical patent/DE3855337D1/de
Application granted granted Critical
Publication of DE3855337T2 publication Critical patent/DE3855337T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
DE3855337T 1987-03-27 1988-03-25 Halbleiterspeichergerät mit verbessertem Redundanzschema Expired - Fee Related DE3855337T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62074905A JP2629697B2 (ja) 1987-03-27 1987-03-27 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3855337D1 true DE3855337D1 (de) 1996-07-11
DE3855337T2 DE3855337T2 (de) 1997-02-06

Family

ID=13560871

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855337T Expired - Fee Related DE3855337T2 (de) 1987-03-27 1988-03-25 Halbleiterspeichergerät mit verbessertem Redundanzschema

Country Status (4)

Country Link
US (1) US4918662A (de)
EP (1) EP0284102B1 (de)
JP (1) JP2629697B2 (de)
DE (1) DE3855337T2 (de)

Families Citing this family (46)

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Publication number Priority date Publication date Assignee Title
US5426607A (en) * 1988-04-27 1995-06-20 Sharp Kabushiki Kaisha Redundant circuit for memory having redundant block operatively connected to special one of normal blocks
US5289417A (en) * 1989-05-09 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with redundancy circuit
JP2547633B2 (ja) * 1989-05-09 1996-10-23 三菱電機株式会社 半導体記憶装置
KR910005601B1 (ko) * 1989-05-24 1991-07-31 삼성전자주식회사 리던던트 블럭을 가지는 반도체 메모리장치
US5471427A (en) * 1989-06-05 1995-11-28 Mitsubishi Denki Kabushiki Kaisha Circuit for repairing defective bit in semiconductor memory device and repairing method
JPH0814985B2 (ja) * 1989-06-06 1996-02-14 富士通株式会社 半導体記憶装置
EP0411626B1 (de) * 1989-08-04 1995-10-25 Fujitsu Limited Halbleiterspeichergerät mit Redundanz
KR920010347B1 (ko) * 1989-12-30 1992-11-27 삼성전자주식회사 분할된 워드라인을 가지는 메모리장치의 리던던시 구조
JPH043399A (ja) * 1990-04-19 1992-01-08 Sharp Corp 半導体記憶装置
US5220518A (en) * 1990-06-07 1993-06-15 Vlsi Technology, Inc. Integrated circuit memory with non-binary array configuration
EP0469571B1 (de) * 1990-07-31 1997-11-12 Texas Instruments Incorporated Redundante Halbleiterspeicheranordnung
JPH04103099A (ja) * 1990-08-23 1992-04-06 Toshiba Corp 半導体記憶装置
KR930008310B1 (ko) * 1991-02-05 1993-08-27 삼성전자 주식회사 반도체 메모리장치의 워드라인드라이버단 배치방법
JPH04322000A (ja) * 1991-04-23 1992-11-11 Hitachi Ltd 半導体記憶装置
US5280607A (en) * 1991-06-28 1994-01-18 International Business Machines Corporation Method and apparatus for tolerating faults in mesh architectures
JP2853406B2 (ja) * 1991-09-10 1999-02-03 日本電気株式会社 半導体記憶装置
US5315558A (en) * 1991-10-25 1994-05-24 Vlsi Technology, Inc. Integrated circuit memory with non-binary array configuration
JP2501993B2 (ja) * 1992-02-24 1996-05-29 株式会社東芝 半導体記憶装置
US5513313A (en) * 1993-01-19 1996-04-30 International Business Machines Corporation Method for generating hierarchical fault-tolerant mesh architectures
JP2967021B2 (ja) * 1993-01-25 1999-10-25 株式会社東芝 半導体メモリ装置
DE69424453T2 (de) * 1993-01-25 2001-04-19 Kabushiki Kaisha Toshiba, Kawasaki Halbleiterspeicheranordnung mit einer Vielzahl von Wortleitungstreiberschaltungen
US5870574A (en) * 1993-04-12 1999-02-09 Silicon Graphics, Inc. System and method for fetching multiple groups of instructions from an instruction cache in a RISC processor system for execution during separate cycles
US5568442A (en) * 1993-05-17 1996-10-22 Silicon Graphics, Inc. RISC processor having improved instruction fetching capability and utilizing address bit predecoding for a segmented cache memory
US5491664A (en) * 1993-09-27 1996-02-13 Cypress Semiconductor Corporation Flexibilitiy for column redundancy in a divided array architecture
JP3351595B2 (ja) * 1993-12-22 2002-11-25 株式会社日立製作所 半導体メモリ装置
US5555212A (en) * 1994-09-19 1996-09-10 Kabushiki Kaisha Toshiba Method and apparatus for redundancy word line replacement in a semiconductor memory device
US5663923A (en) * 1995-04-28 1997-09-02 Intel Corporation Nonvolatile memory blocking architecture
US5841710A (en) * 1997-02-14 1998-11-24 Micron Electronics, Inc. Dynamic address remapping decoder
US6078535A (en) * 1997-10-23 2000-06-20 Texas Instruments Incorporated Redundancy arrangement for novel memory architecture
US6314527B1 (en) 1998-03-05 2001-11-06 Micron Technology, Inc. Recovery of useful areas of partially defective synchronous memory components
US6332183B1 (en) 1998-03-05 2001-12-18 Micron Technology, Inc. Method for recovery of useful areas of partially defective synchronous memory components
US6381707B1 (en) 1998-04-28 2002-04-30 Micron Technology, Inc. System for decoding addresses for a defective memory array
US6381708B1 (en) 1998-04-28 2002-04-30 Micron Technology, Inc. Method for decoding addresses for a defective memory array
JPH11317091A (ja) * 1998-04-30 1999-11-16 Nec Corp 半導体記憶装置
DE19836578C2 (de) * 1998-08-12 2000-08-17 Siemens Ag Integrierter Speicher mit Interblockredundanz
JP4260247B2 (ja) * 1998-09-02 2009-04-30 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
US6134176A (en) * 1998-11-24 2000-10-17 Proebsting; Robert J. Disabling a defective element in an integrated circuit device having redundant elements
US6496876B1 (en) 1998-12-21 2002-12-17 Micron Technology, Inc. System and method for storing a tag to identify a functional storage location in a memory device
US6144610A (en) * 1999-04-20 2000-11-07 Winbond Electronics Corporation Distributed circuits to turn off word lines in a memory array
US6578157B1 (en) 2000-03-06 2003-06-10 Micron Technology, Inc. Method and apparatus for recovery of useful areas of partially defective direct rambus rimm components
US7269765B1 (en) * 2000-04-13 2007-09-11 Micron Technology, Inc. Method and apparatus for storing failing part locations in a module
US6801471B2 (en) * 2002-02-19 2004-10-05 Infineon Technologies Ag Fuse concept and method of operation
WO2005081260A1 (ja) * 2004-02-20 2005-09-01 Spansion Llc 半導体記憶装置および半導体記憶装置の冗長方法
KR100633595B1 (ko) * 2004-04-20 2006-10-12 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동 방법
US7652905B2 (en) * 2007-01-04 2010-01-26 Macronix International Co., Ltd. Flash memory array architecture
JP2010146665A (ja) * 2008-12-19 2010-07-01 Toshiba Corp 抵抗変化型不揮発性半導体メモリ

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051354A (en) * 1975-07-03 1977-09-27 Texas Instruments Incorporated Fault-tolerant cell addressable array
JPS6041463B2 (ja) * 1976-11-19 1985-09-17 株式会社日立製作所 ダイナミツク記憶装置
US4748349A (en) * 1978-09-22 1988-05-31 Texas Instruments Incorporated High performance dynamic sense amplifier with voltage boost for row address lines
JPS58139399A (ja) * 1982-02-15 1983-08-18 Hitachi Ltd 半導体記憶装置
JPS58211393A (ja) * 1982-06-02 1983-12-08 Mitsubishi Electric Corp 半導体メモリ装置
JPS6010492A (ja) * 1983-06-29 1985-01-19 Fujitsu Ltd 半導体記憶装置
US4554646A (en) * 1983-10-17 1985-11-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
JPH0795395B2 (ja) * 1984-02-13 1995-10-11 株式会社日立製作所 半導体集積回路
JPS62202399A (ja) * 1985-10-04 1987-09-07 Mitsubishi Electric Corp 半導体メモリ

Also Published As

Publication number Publication date
EP0284102B1 (de) 1996-06-05
DE3855337T2 (de) 1997-02-06
JPS63241792A (ja) 1988-10-07
EP0284102A3 (de) 1991-05-02
EP0284102A2 (de) 1988-09-28
US4918662A (en) 1990-04-17
JP2629697B2 (ja) 1997-07-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee