DE69224819D1 - Methode zur Herstellung von Halbleiterchips - Google Patents
Methode zur Herstellung von HalbleiterchipsInfo
- Publication number
- DE69224819D1 DE69224819D1 DE69224819T DE69224819T DE69224819D1 DE 69224819 D1 DE69224819 D1 DE 69224819D1 DE 69224819 T DE69224819 T DE 69224819T DE 69224819 T DE69224819 T DE 69224819T DE 69224819 D1 DE69224819 D1 DE 69224819D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor chips
- manufacturing semiconductor
- manufacturing
- chips
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/028—Dicing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4057152A JP2763441B2 (ja) | 1992-02-06 | 1992-02-06 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69224819D1 true DE69224819D1 (de) | 1998-04-23 |
DE69224819T2 DE69224819T2 (de) | 1998-07-09 |
Family
ID=13047598
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69224819T Expired - Fee Related DE69224819T2 (de) | 1992-02-06 | 1992-08-15 | Methode zur Herstellung von Halbleiterchips |
Country Status (4)
Country | Link |
---|---|
US (1) | US5302554A (de) |
EP (1) | EP0558795B1 (de) |
JP (1) | JP2763441B2 (de) |
DE (1) | DE69224819T2 (de) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06268112A (ja) * | 1993-03-10 | 1994-09-22 | Mitsubishi Electric Corp | 半導体装置、及びその製造方法 |
US5580831A (en) * | 1993-07-28 | 1996-12-03 | Fujitsu Limited | Sawcut method of forming alignment marks on two faces of a substrate |
US5552345A (en) * | 1993-09-22 | 1996-09-03 | Harris Corporation | Die separation method for silicon on diamond circuit structures |
JP3374880B2 (ja) * | 1994-10-26 | 2003-02-10 | 三菱電機株式会社 | 半導体装置の製造方法、及び半導体装置 |
US6083811A (en) * | 1996-02-07 | 2000-07-04 | Northrop Grumman Corporation | Method for producing thin dice from fragile materials |
JP3810204B2 (ja) * | 1998-03-19 | 2006-08-16 | 三菱電機株式会社 | 半導体装置の製造方法および半導体装置 |
JP2000077576A (ja) * | 1998-09-02 | 2000-03-14 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
US6320269B1 (en) | 1999-05-03 | 2001-11-20 | Taiwan Semiconductor Manufacturing Company | Method for preparing a semiconductor wafer to receive a protective tape |
JP2000332100A (ja) * | 1999-05-18 | 2000-11-30 | Mitsubishi Electric Corp | 半導体装置の製造方法および半導体装置 |
JP2002092575A (ja) * | 2000-09-19 | 2002-03-29 | Mitsubishi Electric Corp | 小型カードとその製造方法 |
US6291317B1 (en) * | 2000-12-06 | 2001-09-18 | Xerox Corporation | Method for dicing of micro devices |
SG139508A1 (en) * | 2001-09-10 | 2008-02-29 | Micron Technology Inc | Wafer dicing device and method |
SG102639A1 (en) * | 2001-10-08 | 2004-03-26 | Micron Technology Inc | Apparatus and method for packing circuits |
SG142115A1 (en) * | 2002-06-14 | 2008-05-28 | Micron Technology Inc | Wafer level packaging |
SG119185A1 (en) * | 2003-05-06 | 2006-02-28 | Micron Technology Inc | Method for packaging circuits and packaged circuits |
US7210987B2 (en) * | 2004-03-30 | 2007-05-01 | Intel Corporation | Wafer grinding method |
CN100382280C (zh) * | 2005-06-15 | 2008-04-16 | 探微科技股份有限公司 | 晶片切割方法 |
DE102006046789A1 (de) * | 2006-10-02 | 2008-04-03 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zur Herstellung elektronischer Bauteile |
US8647966B2 (en) * | 2011-06-09 | 2014-02-11 | National Semiconductor Corporation | Method and apparatus for dicing die attach film on a semiconductor wafer |
US9165831B2 (en) * | 2013-06-27 | 2015-10-20 | Globalfoundries Inc. | Dice before grind with backside metal |
JP6540430B2 (ja) * | 2015-09-28 | 2019-07-10 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
JP6976111B2 (ja) * | 2017-09-11 | 2021-12-08 | エイブリック株式会社 | 半導体装置の製造方法 |
CN112967928B (zh) * | 2020-12-16 | 2022-07-29 | 重庆康佳光电技术研究院有限公司 | 芯片的切割方法及芯片的转移方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3911559A (en) * | 1973-12-10 | 1975-10-14 | Texas Instruments Inc | Method of dielectric isolation to provide backside collector contact and scribing yield |
US4023258A (en) * | 1976-03-05 | 1977-05-17 | Bell Telephone Laboratories, Incorporated | Method of manufacturing semiconductor diodes for use in millimeter-wave circuits |
JPS56103447A (en) * | 1980-01-22 | 1981-08-18 | Toshiba Corp | Dicing method of semiconductor wafer |
US4946716A (en) * | 1985-05-31 | 1990-08-07 | Tektronix, Inc. | Method of thinning a silicon wafer using a reinforcing material |
JPS6278827A (ja) * | 1985-09-30 | 1987-04-11 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS62122279A (ja) * | 1985-11-22 | 1987-06-03 | Toshiba Corp | 電界効果トランジスタの製造方法 |
US4755474A (en) * | 1986-12-22 | 1988-07-05 | Motorola Inc. | Method of assembling an optocoupler |
JPS63276276A (ja) * | 1987-05-08 | 1988-11-14 | Nec Corp | 半導体装置の製造方法 |
US4904610A (en) * | 1988-01-27 | 1990-02-27 | General Instrument Corporation | Wafer level process for fabricating passivated semiconductor devices |
JPH02148739A (ja) * | 1988-11-29 | 1990-06-07 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US4978639A (en) * | 1989-01-10 | 1990-12-18 | Avantek, Inc. | Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips |
JPH02214127A (ja) * | 1989-02-15 | 1990-08-27 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5071792A (en) * | 1990-11-05 | 1991-12-10 | Harris Corporation | Process for forming extremely thin integrated circuit dice |
US5128282A (en) * | 1991-11-04 | 1992-07-07 | Xerox Corporation | Process for separating image sensor dies and the like from a wafer that minimizes silicon waste |
-
1992
- 1992-02-06 JP JP4057152A patent/JP2763441B2/ja not_active Expired - Lifetime
- 1992-08-11 US US07/928,026 patent/US5302554A/en not_active Expired - Fee Related
- 1992-08-15 DE DE69224819T patent/DE69224819T2/de not_active Expired - Fee Related
- 1992-08-15 EP EP92113942A patent/EP0558795B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5302554A (en) | 1994-04-12 |
EP0558795A1 (de) | 1993-09-08 |
EP0558795B1 (de) | 1998-03-18 |
DE69224819T2 (de) | 1998-07-09 |
JPH05218197A (ja) | 1993-08-27 |
JP2763441B2 (ja) | 1998-06-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |