DE69130624T2 - Verfahren zum Herstellen von Feldeffekt-Transistoren für integrierte Schaltungen - Google Patents

Verfahren zum Herstellen von Feldeffekt-Transistoren für integrierte Schaltungen

Info

Publication number
DE69130624T2
DE69130624T2 DE69130624T DE69130624T DE69130624T2 DE 69130624 T2 DE69130624 T2 DE 69130624T2 DE 69130624 T DE69130624 T DE 69130624T DE 69130624 T DE69130624 T DE 69130624T DE 69130624 T2 DE69130624 T2 DE 69130624T2
Authority
DE
Germany
Prior art keywords
field effect
integrated circuits
effect transistors
manufacturing field
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130624T
Other languages
English (en)
Other versions
DE69130624D1 (de
Inventor
Sailesh Chittipeddi
William Thomas Cochran
Michael James Kelly
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69130624D1 publication Critical patent/DE69130624D1/de
Publication of DE69130624T2 publication Critical patent/DE69130624T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)
DE69130624T 1990-06-26 1991-06-19 Verfahren zum Herstellen von Feldeffekt-Transistoren für integrierte Schaltungen Expired - Fee Related DE69130624T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/543,592 US5045486A (en) 1990-06-26 1990-06-26 Transistor fabrication method

Publications (2)

Publication Number Publication Date
DE69130624D1 DE69130624D1 (de) 1999-01-28
DE69130624T2 true DE69130624T2 (de) 1999-06-17

Family

ID=24168682

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130624T Expired - Fee Related DE69130624T2 (de) 1990-06-26 1991-06-19 Verfahren zum Herstellen von Feldeffekt-Transistoren für integrierte Schaltungen

Country Status (5)

Country Link
US (1) US5045486A (de)
EP (2) EP0771021A3 (de)
JP (1) JP2957757B2 (de)
DE (1) DE69130624T2 (de)
ES (1) ES2127193T3 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202277A (en) * 1989-12-08 1993-04-13 Matsushita Electric Industrial Co., Ltd. Method of fabricating a semiconductor device
US5298446A (en) * 1990-02-20 1994-03-29 Sharp Kabushiki Kaisha Process for producing semiconductor device
US5330925A (en) * 1992-06-18 1994-07-19 At&T Bell Laboratories Method for making a MOS device
JPH07263684A (ja) * 1994-03-25 1995-10-13 Mitsubishi Electric Corp 電界効果トランジスタの製造方法
TW344897B (en) * 1994-11-30 1998-11-11 At&T Tcorporation A process for forming gate oxides possessing different thicknesses on a semiconductor substrate
US5482876A (en) * 1995-05-25 1996-01-09 United Microelectronics Corporation Field effect transistor without spacer mask edge defects
US6033975A (en) * 1997-01-02 2000-03-07 Texas Instruments Incorporated Implant screen and method
US6069042A (en) * 1998-02-13 2000-05-30 Taiwan Semiconductor Manufacturing Company Multi-layer spacer technology for flash EEPROM
US6001690A (en) * 1998-02-13 1999-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming flash EPROM by using iso+aniso silicon nitride spacer etching technology
EP1017087A1 (de) * 1998-12-29 2000-07-05 STMicroelectronics S.r.l. Herstellungsverfahren für einen halbleitersubstratintegrierten MOS-Transistor
US6133131A (en) * 1999-04-19 2000-10-17 United Microelectronics Corp. Method of forming a gate spacer on a semiconductor wafer
DE19920333A1 (de) * 1999-05-03 2000-11-16 Siemens Ag Verfahren zur Herstellung einer Halbleitervorrichtung
US6365471B1 (en) * 1999-06-18 2002-04-02 United Microelectronics Corp. Method for producing PMOS devices
US6426278B1 (en) * 1999-10-07 2002-07-30 International Business Machines Corporation Projection gas immersion laser dopant process (PGILD) fabrication of diffusion halos
US7192836B1 (en) * 1999-11-29 2007-03-20 Advanced Micro Devices, Inc. Method and system for providing halo implant to a semiconductor device with minimal impact to the junction capacitance
US6777300B2 (en) * 2000-12-30 2004-08-17 Texas Instruments Incorporated Method to improve silicide formation on polysilicon
CN100347833C (zh) * 2002-02-01 2007-11-07 Nxp股份有限公司 在一个加工步骤中形成不同厚度的高质量氧化物层的方法
US6803315B2 (en) 2002-08-05 2004-10-12 International Business Machines Corporation Method for blocking implants from the gate of an electronic device via planarizing films
US20070029608A1 (en) * 2005-08-08 2007-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Offset spacers for CMOS transistors
US8373233B2 (en) * 2008-11-13 2013-02-12 Applied Materials, Inc. Highly N-type and P-type co-doping silicon for strain silicon application
US9196708B2 (en) * 2013-12-30 2015-11-24 Taiwan Semiconductor Manufacturing Co., Ltd Method for forming a semiconductor device structure

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378181A (en) * 1976-12-22 1978-07-11 Hitachi Ltd Semiconductor device and its manufacture
JPS53108380A (en) * 1977-03-04 1978-09-21 Hitachi Ltd Semiconductor device
US4382827A (en) * 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
US4422885A (en) * 1981-12-18 1983-12-27 Ncr Corporation Polysilicon-doped-first CMOS process
JPS59188974A (ja) * 1983-04-11 1984-10-26 Nec Corp 半導体装置の製造方法
JPS59193061A (ja) * 1983-04-15 1984-11-01 Hitachi Ltd 半導体装置
US4477310A (en) * 1983-08-12 1984-10-16 Tektronix, Inc. Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas
JPS60241256A (ja) * 1984-05-16 1985-11-30 Hitachi Ltd 半導体装置およびその製造方法
JPS61191070A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 半導体装置の製造方法
JPS6245071A (ja) * 1985-08-22 1987-02-27 Nec Corp 半導体装置の製造方法
JPS6278181A (ja) * 1985-09-30 1987-04-10 興陽産業株式会社 完熟堆肥・有機肥料の製法及び装置
US4760033A (en) * 1986-04-08 1988-07-26 Siemens Aktiengesellschaft Method for the manufacture of complementary MOS field effect transistors in VLSI technology
JPS62241376A (ja) * 1986-04-11 1987-10-22 Seiko Epson Corp Ｍｏｓ型半導体装置の製造方法
US4728617A (en) * 1986-11-04 1988-03-01 Intel Corporation Method of fabricating a MOSFET with graded source and drain regions
JPS63181459A (ja) * 1987-01-23 1988-07-26 Matsushita Electronics Corp 半導体装置の製造方法
US4786609A (en) * 1987-10-05 1988-11-22 North American Philips Corporation, Signetics Division Method of fabricating field-effect transistor utilizing improved gate sidewall spacers
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
JPH02106043A (ja) * 1988-10-14 1990-04-18 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5030582A (en) * 1988-10-14 1991-07-09 Matsushita Electric Industrial Co., Ltd. Method of fabricating a CMOS semiconductor device
US4874713A (en) * 1989-05-01 1989-10-17 Ncr Corporation Method of making asymmetrically optimized CMOS field effect transistors
JPH0770727B2 (ja) * 1989-06-16 1995-07-31 日本電装株式会社 Ｍｉｓトランジスタ及び相補形ｍｉｓトランジスタの製造方法

Also Published As

Publication number Publication date
EP0465045A3 (en) 1992-05-20
DE69130624D1 (de) 1999-01-28
US5045486A (en) 1991-09-03
ES2127193T3 (es) 1999-04-16
EP0465045B1 (de) 1998-12-16
JPH04253341A (ja) 1992-09-09
EP0771021A3 (de) 1998-01-07
JP2957757B2 (ja) 1999-10-06
EP0771021A2 (de) 1997-05-02
EP0465045A2 (de) 1992-01-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee