DE69128888T2 - Programmierbares logisches feld - Google Patents

Programmierbares logisches feld

Info

Publication number
DE69128888T2
DE69128888T2 DE69128888T DE69128888T DE69128888T2 DE 69128888 T2 DE69128888 T2 DE 69128888T2 DE 69128888 T DE69128888 T DE 69128888T DE 69128888 T DE69128888 T DE 69128888T DE 69128888 T2 DE69128888 T2 DE 69128888T2
Authority
DE
Germany
Prior art keywords
cells
array
bus network
bus
interconnected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128888T
Other languages
English (en)
Other versions
DE69128888D1 (de
Inventor
Rafael Camarota
Frederick Furtek
Walford Ho
Edward Browder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Concurrent Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Concurrent Logic Inc filed Critical Concurrent Logic Inc
Publication of DE69128888D1 publication Critical patent/DE69128888D1/de
Application granted granted Critical
Publication of DE69128888T2 publication Critical patent/DE69128888T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
DE69128888T 1990-11-02 1991-11-01 Programmierbares logisches feld Expired - Fee Related DE69128888T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/608,415 US5144166A (en) 1990-11-02 1990-11-02 Programmable logic cell and array
PCT/US1991/008095 WO1992008286A1 (en) 1990-11-02 1991-11-01 Programmable logic cell and array

Publications (2)

Publication Number Publication Date
DE69128888D1 DE69128888D1 (de) 1998-03-12
DE69128888T2 true DE69128888T2 (de) 1998-09-10

Family

ID=24436404

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128888T Expired - Fee Related DE69128888T2 (de) 1990-11-02 1991-11-01 Programmierbares logisches feld

Country Status (8)

Country Link
US (1) US5144166A (de)
EP (1) EP0555353B1 (de)
JP (1) JP3434292B2 (de)
KR (1) KR100202131B1 (de)
AT (1) ATE163113T1 (de)
DE (1) DE69128888T2 (de)
SG (1) SG48079A1 (de)
WO (1) WO1992008286A1 (de)

Families Citing this family (211)

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ATE163113T1 (de) 1998-02-15
WO1992008286A1 (en) 1992-05-14
US5144166A (en) 1992-09-01
EP0555353B1 (de) 1998-02-04
EP0555353A1 (de) 1993-08-18
JP3434292B2 (ja) 2003-08-04
SG48079A1 (en) 1998-04-17
DE69128888D1 (de) 1998-03-12
EP0555353A4 (de) 1994-02-16
JPH06502523A (ja) 1994-03-17
KR930703739A (ko) 1993-11-30
KR100202131B1 (ko) 1999-06-15

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