KR930703739A - 프로그램가능한 논리쎌과 그 배열 - Google Patents

프로그램가능한 논리쎌과 그 배열

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Publication number
KR930703739A
KR930703739A KR1019930701335A KR930701335A KR930703739A KR 930703739 A KR930703739 A KR 930703739A KR 1019930701335 A KR1019930701335 A KR 1019930701335A KR 930701335 A KR930701335 A KR 930701335A KR 930703739 A KR930703739 A KR 930703739A
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South Korea
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logic
array
inputs
input
bus
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KR1019930701335A
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KR100202131B1 (ko
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라펠 씨 카마로타
프레드릭. 씨. 펄테크
월포드 더블유. 호
에드워드 에이치. 브로더
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프레데릭 시. 퍼텍
콘커런트 로직, 인코포레이디드
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Publication of KR100202131B1 publication Critical patent/KR100202131B1/ko

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

본 발명은 2차 행렬 배열로 구성된 쎌(22)과 버스네트워크(12)에 의해 상호연결된 프로그램가능한 논리배열(10)이다.
쎌(22)들은 상,하,좌,우 하나씩의 인접한 4개의 쎌에 의해 직접 연결되어 있다. 각 쎌은 각 8개의 출력과 입력과 8개 입력을 두개의 선으로 연결하는 멀티플렉서와 8개 출력에서 8개 출력 시그날을 만들 수 있도록 도선에 시그날에 대해 연산하는 논리장치로 구성된다. 버스네트워크(12)는 로컬(25), 터닝(26)과 익스프레스 (27)버스로 배열의 각 행열에 제공되며, 주어진 행열에는 버스세그먼트를 형성하기 위해 버스를 분배하는 반복기(24)로 구성된다. 버스네트워크(12)는 개별 선으로써 쎌(22)을 이용하지 않고 배열내 쎌(22)에 자료를 전송할 수 있다.

Description

프로그램가능한 논리쎌과 그 배열
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 버스네트워크와 겹쳐진 쎌의 배열을 예를 들어 설명한 구체적인 구조그림이다, 제2도는 본 발명에 따르는 쎌의 배열을 그림으로 나타낸 것이다, 제3도는 제2도의 쎌 내부구조를 나타낸 도형이다.

Claims (21)

  1. 프로그램될 수 있는 논리 배열의 구성에 있어서, 다수의 논리 쎌로 구성되고, 각 쎌은 배열의 가장자리쎌을 제외하고 4개의 인접 쎌, 즉 좌(또는 서), 우(또는 동), 상(또는 북) 그리고 하(또는 남)에 각각 하나씩을 가지게 되어 논리쎌은 행영 배열이 되고, 각 쎌의 구성에 있어서, 4개의 인접 쎌 각각에서 2개씩 8개의 입력과, 4개의 인접 쎌 각각에서 2개씩 8개의 출력과, 다수의 콘트롤 비트를 저장할 수 있는 장치와, 8개 입력이 제1과 제2 입력선으로 연결되는 멀티플렉스 장치와 입력선에 연결된 입력은 저장장치에 저장된 콘트롤 비트에 의해 기록되고, 그리고 입력선에 시그날과 저장장치에 저장된 콘트롤 비트에 대해 출력에서 시그날을 발생시킬 수 있는 논리장치로 구성된 것을 특징으로 하는 프로그램될 수 있는 논리배열.
  2. 제1항에 있어서, 논리쎌은 인접 쎌에서 각각 두개의 입력을 수용하고 인접 쎌로 각각 두개의 출력을 제공하는 것을 특징으로 하는 장치.
  3. 제1항에 있어서, 4개의 인접 쎌에 연결된 출력과 입력들은 기능적으로 등가인 것을 특징으로 하는 장치.
  4. 제1항에 있어서, 논리장치는 한쌍의 부음 논리함수를 제공하는 것을 특징으로 하는 장치.
  5. 제1항에 있어서, 논리장치는 배타적 오어와 NAND 함수를 제공하는 것을 특징으로 하는 특징으로 하는 장치.
  6. 제1항에 있어서, 논리장치는 플립플톱을 제공하는 것을 특징으로 하는 장치.
  7. 제1항에 있어서, 논리장치는 출력중 하나에 논리 상수 시그날을 제공하는 것을 특징으로 하는 장치.
  8. 제1항에 있어서, 멀티플렉서 장치는 적어도 4개의 입력을 가지는 제1과 제2멀티플렉서의 4개 입력 각각은 인접한 4개의 상이한 쎌에서 유도되고, 제2 멀티플렉스의 4개 입력 각각은 인접한 4개의 쎌에서 유도되는 것을 특징으로 하는 장치.
  9. 제1항에 있어서, 논리장치에는 두개의 출력선이 있는데, 각각이 4개의 출력으로 나누어지는 것을 특징으로 하는 장치.
  10. 제1항에 있어서, 쎌중 적어도 세개는 제1 쎌의 출력이 제2 쎌의 입력에 연결되고 제2 쎌의 출력이 제3쎌의 입력과 연결되고 각 쎌은 입력에 대해 배타적 OR과 논리 NAND함수를 출력에 제공하고 그2쎌은 제1쎌의 입력의 배타적 NOR과 NOR을 출력에 제공하고 제3쎌은 제1쎌의 입력 CR과 AND를 출력에 제공하는 것을 특징으로 하는 장치.
  11. 2차 배열된 논리쎌에서 각 쎌의 행열배열을 위해 배열의 가장자리의 쎌을 제외한 각 쎌에는 행열배열이 되고, 배열내의 시그날을 전송하는 버스 네트워크의 구성에 있어서, 쎌에 의해 형성된 배열의 모든 행열에 로컬버스, 터닝버스와 익스프레스 버스가 제공되고, 버스를 운용하는 반복기 장치가 있고 반복기 장치는 버스 세그먼트를 형성시키기 위해 주어진 행 열의 버스를 분배하고, 각 버스세그먼트는 다수의 논리쎌이 있는 것을 특징으로 하는 2차 배열 논리쎌 장치.
  12. 제11항에 있어서, 버스세그먼트를 형성하는 반복기 장치는 쎌의 배열을 직각 블럭으로 분할하는 행열에 배열되는 것을 특징으로 하는 장치.
  13. 제11항에 있어서, 각 로컬 버스 세그먼트는 쎌과 버스네트워크 사이에 전기적 연결을 제공하기 위해 버스세그먼트에 의해 확장되는 쎌에 연결되는 것을 특징으로 하는 장치.
  14. 제11항에 있어서, 각 터닝세그먼트는 배열의 행과 열사이에서 모든 직각 버스세그먼트에 전기적 연결을 제공하는 것을 특징으로 하는 장치.
  15. 제11항에 있어서, 익스프레스 버스세그먼트는 익스프레스 버스세그먼트를 형성하는 두개의 반복기에만 연결되는 것을 특징으로 하는 장치.
  16. 제11항에 있어서, 반복기 장치는 반복기의 한면에 연결된 버스와 반복기의 다른 한면에 연결된 버스와 연결시키는 프로그램인 것을 특징으로 하는 장치.
  17. 제11항에 있어서, 반복기 장치는 각 프로그램 연결에 전기적 시그날 재생을 제공하는 것을 특징으로 하는 장치.
  18. 제11항에 있어서, 반복기 장치는 주어진 버스 연결을 위한 반복기 장치를 통해 전기적 시그날 방향을 선택할 수 있도록 프로그램인 것을 특징으로 하는 장치.
  19. 프로그램할 수 있는 논리배열의 구성에 있어서; 다수의 논리쎌이 행열로 배열되기 위해 배열의 가장자리 쎌을 제외한 각 쎌에 좌(또는 서), 우(또는 동), 상(또는 북), 하(또는 남)에 각각 인접한 4개의 쎌을 가지고, 논리셀에 독립적 타이밍 시그날을 제공하기 위해 클럭 분포 장치가 있으며, 이장치는 배열의 각 컬럼에 있는 하나의 멀티플렉스로 구성되고, 각 멀티플렉서는 다수의 입력과 하나의 출력을 가지며, 출력은 주어진 컬럼에서 각 하나의 논리쎌과 연결된 것을 특징으로 하는 장치.
  20. 제19항에 있어서, 클럭 분배장치에 있는 멀티플렉서는 4개의 입력을 가지고 제1입력을 논리상수 시그날로 멀티플레서에 제공되고 제2 입력을 외부 타이밍 소스에서 제공되고, 제3입력은 익스프레스 버스에서 제4입력은 논리 쎌의 출력에서 제공되는 것을 특징으로 하는 장치.
  21. 제19항에서 배열에서 주어진 컬럼의 논리쎌을 제공되는 타이밍 시그날을 배열의 다른 컬럼의 타이밍 시그날과는 독립적인 것을 특징으로 하는 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930701335A 1990-11-02 1991-11-01 프로그램 가능한 논리쎌과 그 배열 KR100202131B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/608,415 US5144166A (en) 1990-11-02 1990-11-02 Programmable logic cell and array
US608,415 1990-11-02
PCT/US1991/008095 WO1992008286A1 (en) 1990-11-02 1991-11-01 Programmable logic cell and array

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KR930703739A true KR930703739A (ko) 1993-11-30
KR100202131B1 KR100202131B1 (ko) 1999-06-15

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US (1) US5144166A (ko)
EP (1) EP0555353B1 (ko)
JP (1) JP3434292B2 (ko)
KR (1) KR100202131B1 (ko)
AT (1) ATE163113T1 (ko)
DE (1) DE69128888T2 (ko)
SG (1) SG48079A1 (ko)
WO (1) WO1992008286A1 (ko)

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