DE69128446D1 - Sehr schnelle redundante Zeilen und Spalten für Halbleiter-Speicher - Google Patents

Sehr schnelle redundante Zeilen und Spalten für Halbleiter-Speicher

Info

Publication number
DE69128446D1
DE69128446D1 DE69128446T DE69128446T DE69128446D1 DE 69128446 D1 DE69128446 D1 DE 69128446D1 DE 69128446 T DE69128446 T DE 69128446T DE 69128446 T DE69128446 T DE 69128446T DE 69128446 D1 DE69128446 D1 DE 69128446D1
Authority
DE
Germany
Prior art keywords
columns
semiconductor memory
redundant rows
fast
fast redundant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128446T
Other languages
English (en)
Other versions
DE69128446T2 (de
Inventor
Robert J Proebsting
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intergraph Corp
Original Assignee
Intergraph Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intergraph Corp filed Critical Intergraph Corp
Application granted granted Critical
Publication of DE69128446D1 publication Critical patent/DE69128446D1/de
Publication of DE69128446T2 publication Critical patent/DE69128446T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
DE69128446T 1990-09-28 1991-09-21 Sehr schnelle redundante Zeilen und Spalten für Halbleiter-Speicher Expired - Fee Related DE69128446T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/590,243 US5274593A (en) 1990-09-28 1990-09-28 High speed redundant rows and columns for semiconductor memories

Publications (2)

Publication Number Publication Date
DE69128446D1 true DE69128446D1 (de) 1998-01-29
DE69128446T2 DE69128446T2 (de) 1998-07-02

Family

ID=24361452

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128446T Expired - Fee Related DE69128446T2 (de) 1990-09-28 1991-09-21 Sehr schnelle redundante Zeilen und Spalten für Halbleiter-Speicher

Country Status (4)

Country Link
US (1) US5274593A (de)
EP (1) EP0477809B1 (de)
JP (1) JPH07122096A (de)
DE (1) DE69128446T2 (de)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2695493B1 (fr) * 1992-09-08 1994-10-07 Thomson Composants Militaires Circuit de mémoire avec redondance.
US5498975A (en) * 1992-11-19 1996-03-12 Altera Corporation Implementation of redundancy on a programmable logic device
US5557618A (en) * 1993-01-19 1996-09-17 Tektronix, Inc. Signal sampling circuit with redundancy
JPH08508837A (ja) * 1993-06-02 1996-09-17 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 冗長チャネル・バスの多重化装置
DE4447603C2 (de) * 1993-09-29 1998-02-19 Mitsubishi Electric Corp Schaltung zum Erzeugen einer Referenzspannung
JPH07153296A (ja) * 1993-11-26 1995-06-16 Nec Corp 半導体記憶装置
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
WO2002029600A2 (de) 2000-10-06 2002-04-11 Pact Informationstechnologie Gmbh Zellenarordnung mit segmentierterwischenzellstruktur
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654593A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
DE19654846A1 (de) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (de) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704742A1 (de) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
KR100252053B1 (ko) 1997-12-04 2000-05-01 윤종용 칼럼 방향의 데이터 입출력선을 가지는 반도체메모리장치와불량셀 구제회로 및 방법
DE19861088A1 (de) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
JP4519208B2 (ja) * 1998-03-03 2010-08-04 株式会社東芝 半導体記憶装置
JP3206541B2 (ja) * 1998-03-04 2001-09-10 日本電気株式会社 半導体記憶装置
JP3178430B2 (ja) * 1998-09-16 2001-06-18 日本電気株式会社 半導体記憶装置
JP2000182390A (ja) 1998-12-11 2000-06-30 Mitsubishi Electric Corp 半導体記憶装置
WO2002013000A2 (de) 2000-06-13 2002-02-14 Pact Informationstechnologie Gmbh Pipeline ct-protokolle und -kommunikation
AU5805300A (en) 1999-06-10 2001-01-02 Pact Informationstechnologie Gmbh Sequence partitioning in cell structures
US6122208A (en) * 1999-09-17 2000-09-19 Rambus Inc. Circuit and method for column redundancy for high bandwidth memories
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7483828B2 (en) * 2001-03-16 2009-01-27 Meaningful Machines, L.L.C. Multilingual database creation system and method
EP2224330B1 (de) 2001-06-20 2012-05-09 Krass, Maren Verfahren und gerät zum partitionieren von grossen rechnerprogrammen
US6966012B1 (en) * 2001-06-22 2005-11-15 Artisan Components, Inc. Memory column redundancy circuitry and method for implementing the same
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
WO2003060747A2 (de) 2002-01-19 2003-07-24 Pact Xpp Technologies Ag Reconfigurierbarer prozessor
US8127061B2 (en) 2002-02-18 2012-02-28 Martin Vorbach Bus systems and reconfiguration methods
US6803782B2 (en) * 2002-03-21 2004-10-12 John Conrad Koob Arrayed processing element redundancy architecture
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
WO2004038599A1 (de) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Rekonfigurierbare sequenzerstruktur
US7185225B2 (en) * 2002-12-02 2007-02-27 Marvell World Trade Ltd. Self-reparable semiconductor and method thereof
JP4700611B2 (ja) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
EP1974265A1 (de) 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardwaredefinitionsverfahren
JP2007257791A (ja) * 2006-03-24 2007-10-04 Fujitsu Ltd 半導体記憶装置
US7724169B2 (en) * 2008-02-12 2010-05-25 National Semiconductor Corporation Semiconductor chip with a number of A/D converters that include a group of redundant A/D converters
US7881134B2 (en) * 2008-11-17 2011-02-01 Micron Technology, Inc. Replacing defective columns of memory cells in response to external addresses
US8964493B2 (en) * 2013-01-04 2015-02-24 International Business Machines Corporation Defective memory column replacement with load isolation
US10146719B2 (en) * 2017-03-24 2018-12-04 Micron Technology, Inc. Semiconductor layered device with data bus
US10964702B2 (en) 2018-10-17 2021-03-30 Micron Technology, Inc. Semiconductor device with first-in-first-out circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59144098A (ja) * 1983-02-08 1984-08-17 Fujitsu Ltd 半導体記憶装置
US4566102A (en) * 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US4598388A (en) * 1985-01-22 1986-07-01 Texas Instruments Incorporated Semiconductor memory with redundant column circuitry
US5134584A (en) * 1988-07-22 1992-07-28 Vtc Incorporated Reconfigurable memory

Also Published As

Publication number Publication date
EP0477809B1 (de) 1997-12-17
DE69128446T2 (de) 1998-07-02
EP0477809A2 (de) 1992-04-01
JPH07122096A (ja) 1995-05-12
EP0477809A3 (en) 1994-12-21
US5274593A (en) 1993-12-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: INTERGRAPH HARDWARE TECHNOLOGIES CO., LAS VEGAS, N

8339 Ceased/non-payment of the annual fee