DE68920233T2 - Steuerschaltung für eine Halbleiterspeicheranordnung und Halbleiterspeichersystem. - Google Patents

Steuerschaltung für eine Halbleiterspeicheranordnung und Halbleiterspeichersystem.

Info

Publication number
DE68920233T2
DE68920233T2 DE68920233T DE68920233T DE68920233T2 DE 68920233 T2 DE68920233 T2 DE 68920233T2 DE 68920233 T DE68920233 T DE 68920233T DE 68920233 T DE68920233 T DE 68920233T DE 68920233 T2 DE68920233 T2 DE 68920233T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
control circuit
memory device
memory system
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68920233T
Other languages
English (en)
Other versions
DE68920233D1 (de
Inventor
Takashi C O Intellectua Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE68920233D1 publication Critical patent/DE68920233D1/de
Application granted granted Critical
Publication of DE68920233T2 publication Critical patent/DE68920233T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE68920233T 1988-08-26 1989-08-24 Steuerschaltung für eine Halbleiterspeicheranordnung und Halbleiterspeichersystem. Expired - Fee Related DE68920233T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21182788 1988-08-26

Publications (2)

Publication Number Publication Date
DE68920233D1 DE68920233D1 (de) 1995-02-09
DE68920233T2 true DE68920233T2 (de) 1995-05-24

Family

ID=16612249

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68920233T Expired - Fee Related DE68920233T2 (de) 1988-08-26 1989-08-24 Steuerschaltung für eine Halbleiterspeicheranordnung und Halbleiterspeichersystem.

Country Status (4)

Country Link
US (2) US5031150A (de)
EP (1) EP0355828B1 (de)
KR (1) KR930008641B1 (de)
DE (1) DE68920233T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2614514B2 (ja) * 1989-05-19 1997-05-28 三菱電機株式会社 ダイナミック・ランダム・アクセス・メモリ
USRE38379E1 (en) * 1989-08-28 2004-01-06 Hitachi, Ltd. Semiconductor memory with alternately multiplexed row and column addressing
JPH0461096A (ja) * 1990-06-29 1992-02-27 Matsushita Electric Ind Co Ltd メモリー制御装置
GB2247794A (en) * 1990-09-07 1992-03-11 Samsung Electronics Co Ltd Control circuits
US5258952A (en) * 1990-12-14 1993-11-02 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with separate time-out control for read and write operations
US5274591A (en) * 1992-08-13 1993-12-28 Micron Technology, Inc. Serial clock noise immunity in a semiconductor memory integrated circuit having a serial port
US5383155A (en) * 1993-11-08 1995-01-17 International Business Machines Corporation Data output latch control circuit and process for semiconductor memory system
JP3222684B2 (ja) * 1994-04-20 2001-10-29 株式会社東芝 半導体記憶装置
JPH08102187A (ja) * 1994-09-29 1996-04-16 Toshiba Microelectron Corp ダイナミック型メモリ
KR100200763B1 (ko) * 1996-11-30 1999-06-15 윤종용 반도체 메모리 장치의 컬럼 선택 라인 인에이블 회로
US5903512A (en) * 1996-12-30 1999-05-11 Siemens Aktiengesellschaft Circuit and method to externally adjust internal circuit timing
JP3341710B2 (ja) 1999-05-14 2002-11-05 日本電気株式会社 半導体記憶装置
KR100300079B1 (ko) * 1999-07-28 2001-11-01 김영환 센스앰프 구동회로
KR100355229B1 (ko) * 2000-01-28 2002-10-11 삼성전자 주식회사 카스 명령의 동작 지연 기능을 구비한 반도체 메모리 장치및 이에 적용되는 버퍼와 신호전송 회로
KR100970517B1 (ko) * 2002-07-31 2010-07-16 엔엑스피 비 브이 데이터 처리 회로, 이미지 처리 시스템, 수신기 디코더장치 및 통신 네트워크
US9840417B2 (en) 2008-07-31 2017-12-12 Korea Institute Of Science And Technology AA′ stacked graphite

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052513B2 (ja) * 1981-12-02 1985-11-19 富士通株式会社 半導体記憶装置
JPS59135695A (ja) * 1983-01-24 1984-08-03 Mitsubishi Electric Corp 半導体記憶装置
US4596004A (en) * 1983-09-14 1986-06-17 International Business Machines Corporation High speed memory with a multiplexed address bus
US4656612A (en) * 1984-11-19 1987-04-07 Inmos Corporation Dram current control technique
JPS61284892A (ja) * 1985-06-11 1986-12-15 Ascii Corp 記憶装置
JPS62134894A (ja) * 1985-12-06 1987-06-17 Mitsubishi Electric Corp 半導体記憶装置
JPS6355797A (ja) * 1986-08-27 1988-03-10 Fujitsu Ltd メモリ
JPH0812760B2 (ja) * 1986-11-29 1996-02-07 三菱電機株式会社 ダイナミックメモリ装置
JPH07107797B2 (ja) * 1987-02-10 1995-11-15 三菱電機株式会社 ダイナミツクランダムアクセスメモリ
JP2590122B2 (ja) * 1987-08-07 1997-03-12 富士通株式会社 半導体メモリ
US5384745A (en) * 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device

Also Published As

Publication number Publication date
EP0355828A3 (de) 1992-03-04
DE68920233D1 (de) 1995-02-09
EP0355828B1 (de) 1994-12-28
KR930008641B1 (ko) 1993-09-11
USRE35065E (en) 1995-10-17
US5031150A (en) 1991-07-09
EP0355828A2 (de) 1990-02-28
KR900003898A (ko) 1990-03-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee