DE69115341D1 - Verfahren zur Herstellung einer DRAM-Zelle mit gestapeltem Kondensator - Google Patents

Verfahren zur Herstellung einer DRAM-Zelle mit gestapeltem Kondensator

Info

Publication number
DE69115341D1
DE69115341D1 DE69115341T DE69115341T DE69115341D1 DE 69115341 D1 DE69115341 D1 DE 69115341D1 DE 69115341 T DE69115341 T DE 69115341T DE 69115341 T DE69115341 T DE 69115341T DE 69115341 D1 DE69115341 D1 DE 69115341D1
Authority
DE
Germany
Prior art keywords
making
dram cell
stacked capacitor
capacitor dram
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69115341T
Other languages
English (en)
Other versions
DE69115341T2 (de
Inventor
Tsui Chiu Chan
Frank Randolph Bryant
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69115341D1 publication Critical patent/DE69115341D1/de
Publication of DE69115341T2 publication Critical patent/DE69115341T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/911—Light sensitive array adapted to be scanned by electron beam, e.g. vidicon device

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
DE69115341T 1990-04-30 1991-03-25 Verfahren zur Herstellung einer DRAM-Zelle mit gestapeltem Kondensator Expired - Fee Related DE69115341T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/516,271 US5006481A (en) 1989-11-30 1990-04-30 Method of making a stacked capacitor DRAM cell

Publications (2)

Publication Number Publication Date
DE69115341D1 true DE69115341D1 (de) 1996-01-25
DE69115341T2 DE69115341T2 (de) 1996-05-09

Family

ID=24054856

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69115341T Expired - Fee Related DE69115341T2 (de) 1990-04-30 1991-03-25 Verfahren zur Herstellung einer DRAM-Zelle mit gestapeltem Kondensator

Country Status (5)

Country Link
US (1) US5006481A (de)
EP (1) EP0455340B1 (de)
JP (1) JP2971972B2 (de)
KR (1) KR910019237A (de)
DE (1) DE69115341T2 (de)

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KR920001716A (ko) * 1990-06-05 1992-01-30 김광호 디램셀의 적층형 캐패시터의 구조 및 제조방법
JPH0449654A (ja) * 1990-06-19 1992-02-19 Nec Corp 半導体メモリ
KR930007192B1 (ko) * 1990-06-29 1993-07-31 삼성전자 주식회사 디램셀의 적층형캐패시터 및 제조방법
US7335570B1 (en) 1990-07-24 2008-02-26 Semiconductor Energy Laboratory Co., Ltd. Method of forming insulating films, capacitances, and semiconductor devices
EP0468758B1 (de) * 1990-07-24 1997-03-26 Semiconductor Energy Laboratory Co., Ltd. Verfahren zum Herstellen isolierender Filme, Kapazitäten und Halbleiteranordnungen
US5170233A (en) * 1991-03-19 1992-12-08 Micron Technology, Inc. Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor
JPH05183121A (ja) * 1991-04-01 1993-07-23 Fujitsu Ltd 半導体装置とその製造方法
JP2797746B2 (ja) * 1991-04-05 1998-09-17 日本電気株式会社 集積回路用容量素子の製作方法
KR930010081B1 (ko) * 1991-05-24 1993-10-14 현대전자산업 주식회사 2중 적층캐패시터 구조를 갖는 반도체 기억장치 및 그 제조방법
US5223448A (en) * 1991-07-18 1993-06-29 Industrial Technology Research Institute Method for producing a layered capacitor structure for a dynamic random access memory device
JP3055242B2 (ja) * 1991-09-19 2000-06-26 日本電気株式会社 半導体装置およびその製造方法
US5168073A (en) * 1991-10-31 1992-12-01 Micron Technology, Inc. Method for fabricating storage node capacitor having tungsten and etched tin storage node capacitor plate
US5192703A (en) * 1991-10-31 1993-03-09 Micron Technology, Inc. Method of making tungsten contact core stack capacitor
US5472900A (en) * 1991-12-31 1995-12-05 Intel Corporation Capacitor fabricated on a substrate containing electronic circuitry
US5973910A (en) * 1991-12-31 1999-10-26 Intel Corporation Decoupling capacitor in an integrated circuit
US5401680A (en) * 1992-02-18 1995-03-28 National Semiconductor Corporation Method for forming a ceramic oxide capacitor having barrier layers
KR950011636B1 (ko) * 1992-03-04 1995-10-07 금성일렉트론주식회사 개선된 레이아웃을 갖는 다이내믹 랜덤 액세스 메모리와 그것의 메모리셀 배치방법
JP2802470B2 (ja) * 1992-03-12 1998-09-24 三菱電機株式会社 半導体装置およびその製造方法
US5356834A (en) * 1992-03-24 1994-10-18 Kabushiki Kaisha Toshiba Method of forming contact windows in semiconductor devices
KR960013508B1 (ko) * 1992-07-07 1996-10-05 현대전자산업 주식회사 반도체 기억장치 및 그 제조방법
JPH06209085A (ja) * 1992-07-23 1994-07-26 Texas Instr Inc <Ti> スタック形ｄｒａｍコンデンサ構造体とその製造方法
US5563089A (en) * 1994-07-20 1996-10-08 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
US5369048A (en) * 1993-08-26 1994-11-29 United Microelectronics Corporation Stack capacitor DRAM cell with buried bit-line and method of manufacture
KR970011761B1 (ko) * 1994-04-12 1997-07-15 엘지반도체 주식회사 반도체 디램 셀 및 디램셀의 캐패시터 제조 방법
JP3474332B2 (ja) * 1994-10-11 2003-12-08 台灣茂▲夕▼電子股▲分▼有限公司 Ｄｒａｍ用の自己調整されたキャパシタ底部プレート・ローカル相互接続方法
US5457065A (en) * 1994-12-14 1995-10-10 United Microelectronics Corporation method of manufacturing a new DRAM capacitor structure having increased capacitance
JP3160198B2 (ja) * 1995-02-08 2001-04-23 インターナショナル・ビジネス・マシーンズ・コーポレ−ション デカップリング・コンデンサが形成された半導体基板及びこれの製造方法
US5661064A (en) 1995-11-13 1997-08-26 Micron Technology, Inc. Method of forming a capacitor having container members
US5637523A (en) * 1995-11-20 1997-06-10 Micron Technology, Inc. Method of forming a capacitor and a capacitor construction
US6218237B1 (en) 1996-01-03 2001-04-17 Micron Technology, Inc. Method of forming a capacitor
US5754390A (en) * 1996-01-23 1998-05-19 Micron Technology, Inc. Integrated capacitor bottom electrode for use with conformal dielectric
US5858832A (en) * 1996-03-11 1999-01-12 Chartered Semiconduction Manufacturing Ltd. Method for forming a high areal capacitance planar capacitor
US5970358A (en) * 1997-06-30 1999-10-19 Micron Technology, Inc. Method for forming a capacitor wherein the first capacitor plate includes electrically coupled conductive layers separated by an intervening insulative layer
US6048763A (en) 1997-08-21 2000-04-11 Micron Technology, Inc. Integrated capacitor bottom electrode with etch stop layer
US5920763A (en) * 1997-08-21 1999-07-06 Micron Technology, Inc. Method and apparatus for improving the structural integrity of stacked capacitors
US6214687B1 (en) 1999-02-17 2001-04-10 Micron Technology, Inc. Method of forming a capacitor and a capacitor construction
GB2367428B (en) * 2001-12-19 2002-10-09 Zarlink Semiconductor Ltd Integrated circuit
US8169014B2 (en) 2006-01-09 2012-05-01 Taiwan Semiconductor Manufacturing Co., Ltd. Interdigitated capacitive structure for an integrated circuit
US11322500B2 (en) 2020-07-28 2022-05-03 HeFeChip Corporation Limited Stacked capacitor with horizontal and vertical fin structures and method for making the same

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US4475118A (en) * 1978-12-21 1984-10-02 National Semiconductor Corporation Dynamic MOS RAM with storage cells having a mainly insulated first plate
JPS5623771A (en) * 1979-08-01 1981-03-06 Hitachi Ltd Semiconductor memory
JPS5832789B2 (ja) * 1980-07-18 1983-07-15 富士通株式会社 半導体メモリ
US4403394A (en) * 1980-12-17 1983-09-13 International Business Machines Corporation Formation of bit lines for ram device
JPS602784B2 (ja) * 1982-12-20 1985-01-23 富士通株式会社 半導体記憶装置
JPS6074470A (ja) * 1983-09-29 1985-04-26 Fujitsu Ltd 半導体装置
JPS61183952A (ja) * 1985-02-09 1986-08-16 Fujitsu Ltd 半導体記憶装置及びその製造方法
US4855801A (en) * 1986-08-22 1989-08-08 Siemens Aktiengesellschaft Transistor varactor for dynamics semiconductor storage means
DE3856143T2 (de) * 1987-06-17 1998-10-29 Fujitsu Ltd Verfahren zum Herstellen einer dynamischen Speicherzelle mit wahlfreiem Zugriff
JPS6454551A (en) * 1987-08-25 1989-03-02 Nec Corp Work area securing/batch returning system
JPS6454552A (en) * 1987-08-26 1989-03-02 Oki Electric Ind Co Ltd Data transfer system
JPH01154551A (ja) * 1987-12-11 1989-06-16 Oki Electric Ind Co Ltd 半導体メモリ集積回路装置及びその製造方法

Also Published As

Publication number Publication date
JP2971972B2 (ja) 1999-11-08
DE69115341T2 (de) 1996-05-09
US5006481A (en) 1991-04-09
EP0455340B1 (de) 1995-12-13
KR910019237A (ko) 1991-11-30
EP0455340A1 (de) 1991-11-06
JPH05326872A (ja) 1993-12-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee