DE69105530D1 - Halbleiterscheibe. - Google Patents
Halbleiterscheibe.Info
- Publication number
- DE69105530D1 DE69105530D1 DE69105530T DE69105530T DE69105530D1 DE 69105530 D1 DE69105530 D1 DE 69105530D1 DE 69105530 T DE69105530 T DE 69105530T DE 69105530 T DE69105530 T DE 69105530T DE 69105530 D1 DE69105530 D1 DE 69105530D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor wafer
- wafer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Dicing (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP958290A JPH0758725B2 (ja) | 1990-01-19 | 1990-01-19 | 半導体ウェハ |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69105530D1 true DE69105530D1 (de) | 1995-01-19 |
DE69105530T2 DE69105530T2 (de) | 1995-05-04 |
Family
ID=11724307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69105530T Expired - Fee Related DE69105530T2 (de) | 1990-01-19 | 1991-01-16 | Halbleiterscheibe. |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0438127B1 (de) |
JP (1) | JPH0758725B2 (de) |
KR (1) | KR940010641B1 (de) |
DE (1) | DE69105530T2 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0678904A1 (de) * | 1994-04-12 | 1995-10-25 | Lsi Logic Corporation | Wafer-Schneidverfahren durch Mehrfachschnitte |
JPH07302773A (ja) * | 1994-05-06 | 1995-11-14 | Texas Instr Japan Ltd | 半導体ウエハ及び半導体装置 |
EP0767492A3 (de) * | 1995-10-02 | 1998-09-09 | Altera Corporation | Testsystem integrierter Schaltungen |
US6020758A (en) * | 1996-03-11 | 2000-02-01 | Altera Corporation | Partially reconfigurable programmable logic device |
JPH09252034A (ja) * | 1996-03-18 | 1997-09-22 | Mitsubishi Electric Corp | 半導体ウエハ,半導体装置及び半導体装置の製造方法 |
JP2001135597A (ja) * | 1999-08-26 | 2001-05-18 | Fujitsu Ltd | 半導体装置の製造方法 |
ATE334479T1 (de) * | 2000-07-21 | 2006-08-15 | Koninkl Philips Electronics Nv | VERFAHREN ZUR HERSTELLUNG INTEGRIERTER SCHALTUNGEN MIT VERBESSERTEN LEITERBAHNEN IN SOGENANNTER ßSÄGEBÜGELß-FORM |
JP4631572B2 (ja) * | 2005-07-14 | 2011-02-16 | セイコーエプソン株式会社 | 液滴吐出ヘッド |
JP2013187402A (ja) | 2012-03-08 | 2013-09-19 | Mitsubishi Electric Corp | 半導体ウェハ及びその検査方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3849872A (en) * | 1972-10-24 | 1974-11-26 | Ibm | Contacting integrated circuit chip terminal through the wafer kerf |
JPH0530361Y2 (de) * | 1988-02-23 | 1993-08-03 | ||
JPH01276735A (ja) * | 1988-04-28 | 1989-11-07 | Fuji Electric Co Ltd | 集積回路素子ウエハ |
-
1990
- 1990-01-19 JP JP958290A patent/JPH0758725B2/ja not_active Expired - Lifetime
-
1991
- 1991-01-16 DE DE69105530T patent/DE69105530T2/de not_active Expired - Fee Related
- 1991-01-16 EP EP91100434A patent/EP0438127B1/de not_active Expired - Lifetime
- 1991-01-18 KR KR1019910000768A patent/KR940010641B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0438127A2 (de) | 1991-07-24 |
EP0438127B1 (de) | 1994-12-07 |
KR910015039A (ko) | 1991-08-31 |
EP0438127A3 (en) | 1992-03-04 |
DE69105530T2 (de) | 1995-05-04 |
JPH03214638A (ja) | 1991-09-19 |
KR940010641B1 (ko) | 1994-10-24 |
JPH0758725B2 (ja) | 1995-06-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |