DE69114555D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE69114555D1
DE69114555D1 DE69114555T DE69114555T DE69114555D1 DE 69114555 D1 DE69114555 D1 DE 69114555D1 DE 69114555 T DE69114555 T DE 69114555T DE 69114555 T DE69114555 T DE 69114555T DE 69114555 D1 DE69114555 D1 DE 69114555D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69114555T
Other languages
English (en)
Other versions
DE69114555T2 (de
Inventor
Yasushi Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69114555D1 publication Critical patent/DE69114555D1/de
Application granted granted Critical
Publication of DE69114555T2 publication Critical patent/DE69114555T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
DE69114555T 1990-03-19 1991-03-18 Halbleiterspeicheranordnung. Expired - Fee Related DE69114555T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2069215A JPH0834058B2 (ja) 1990-03-19 1990-03-19 半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE69114555D1 true DE69114555D1 (de) 1995-12-21
DE69114555T2 DE69114555T2 (de) 1996-07-04

Family

ID=13396275

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69114555T Expired - Fee Related DE69114555T2 (de) 1990-03-19 1991-03-18 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US5245581A (de)
EP (1) EP0448025B1 (de)
JP (1) JPH0834058B2 (de)
KR (1) KR940009082B1 (de)
DE (1) DE69114555T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5861767A (en) * 1996-12-03 1999-01-19 Cirrus Logic, Inc. Digital step generators and circuits, systems and methods using the same
US5912853A (en) * 1996-12-03 1999-06-15 Cirrus Logic, Inc. Precision sense amplifiers and memories, systems and methods using the same
JP2007120991A (ja) * 2005-10-25 2007-05-17 Sharp Corp テストパターンの検出率算出方法、コンピュータプログラム及びテストパターンの検出率算出装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0787037B2 (ja) * 1984-03-02 1995-09-20 沖電気工業株式会社 半導体メモリ回路のデータ書込方法
US4791616A (en) * 1985-07-10 1988-12-13 Fujitsu Limited Semiconductor memory device
JPS62232796A (ja) * 1986-04-01 1987-10-13 Toshiba Corp 半導体記憶装置
JPH0758592B2 (ja) * 1987-11-30 1995-06-21 日本電気株式会社 半導体メモリ
JP2644261B2 (ja) * 1988-03-15 1997-08-25 株式会社東芝 ダイナミック型半導体記憶装置
KR910009444B1 (ko) * 1988-12-20 1991-11-16 삼성전자 주식회사 반도체 메모리 장치

Also Published As

Publication number Publication date
JPH03269895A (ja) 1991-12-02
EP0448025A3 (de) 1994-02-02
US5245581A (en) 1993-09-14
DE69114555T2 (de) 1996-07-04
EP0448025A2 (de) 1991-09-25
KR940009082B1 (ko) 1994-09-29
EP0448025B1 (de) 1995-11-15
JPH0834058B2 (ja) 1996-03-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: PATENTANWAELTE MUELLER & HOFFMANN, 81667 MUENCHEN

8339 Ceased/non-payment of the annual fee