DE69031527T2 - Pipelinefehlerprüfung und Korrektur für Cache-Speicher - Google Patents

Pipelinefehlerprüfung und Korrektur für Cache-Speicher

Info

Publication number
DE69031527T2
DE69031527T2 DE69031527T DE69031527T DE69031527T2 DE 69031527 T2 DE69031527 T2 DE 69031527T2 DE 69031527 T DE69031527 T DE 69031527T DE 69031527 T DE69031527 T DE 69031527T DE 69031527 T2 DE69031527 T2 DE 69031527T2
Authority
DE
Germany
Prior art keywords
port
cache
technique
array
port array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69031527T
Other languages
English (en)
Other versions
DE69031527D1 (de
Inventor
Hu Herbert Chao
Jung-Herng Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69031527D1 publication Critical patent/DE69031527D1/de
Application granted granted Critical
Publication of DE69031527T2 publication Critical patent/DE69031527T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0853—Cache with multiport tag or data arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
DE69031527T 1989-09-19 1990-03-20 Pipelinefehlerprüfung und Korrektur für Cache-Speicher Expired - Fee Related DE69031527T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/409,362 US5058116A (en) 1989-09-19 1989-09-19 Pipelined error checking and correction for cache memories

Publications (2)

Publication Number Publication Date
DE69031527D1 DE69031527D1 (de) 1997-11-06
DE69031527T2 true DE69031527T2 (de) 1998-03-26

Family

ID=23620151

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031527T Expired - Fee Related DE69031527T2 (de) 1989-09-19 1990-03-20 Pipelinefehlerprüfung und Korrektur für Cache-Speicher

Country Status (4)

Country Link
US (1) US5058116A (de)
EP (1) EP0418457B1 (de)
JP (1) JPH03108041A (de)
DE (1) DE69031527T2 (de)

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US5359722A (en) * 1990-07-23 1994-10-25 International Business Machines Corporation Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM
US5233616A (en) * 1990-10-01 1993-08-03 Digital Equipment Corporation Write-back cache with ECC protection
US5274799A (en) * 1991-01-04 1993-12-28 Array Technology Corporation Storage device array architecture with copyback cache
JPH04290144A (ja) * 1991-03-19 1992-10-14 Hitachi Ltd メモリ拡張方式
US5325375A (en) * 1991-06-28 1994-06-28 Sun Microsystems, Inc. Method and apparatus for non-atomic level parity protection for storing data in a random access memory
US5455939A (en) * 1992-06-17 1995-10-03 Intel Corporation Method and apparatus for error detection and correction of data transferred between a CPU and system memory
US5493574A (en) * 1992-09-24 1996-02-20 Zilog, Inc. Power efficient RAM disk and a method of emulating a rotating memory disk
US5438575A (en) * 1992-11-16 1995-08-01 Ampex Corporation Data storage system with stale data detector and method of operation
JPH0756815A (ja) * 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> キャッシュ動作方法及びキャッシュ
JPH08106733A (ja) * 1994-10-07 1996-04-23 Hitachi Ltd 情報記憶媒体利用システム
US5687353A (en) * 1995-03-03 1997-11-11 Hal Computer Systems, Inc. Merging data using a merge code from a look-up table and performing ECC generation on the merged data
JP3782840B2 (ja) 1995-07-14 2006-06-07 株式会社ルネサステクノロジ 外部記憶装置およびそのメモリアクセス制御方法
US5805787A (en) * 1995-12-29 1998-09-08 Emc Corporation Disk based disk cache interfacing system and method
US5724501A (en) * 1996-03-29 1998-03-03 Emc Corporation Quick recovery of write cache in a fault tolerant I/O system
US5774648A (en) * 1996-10-02 1998-06-30 Mitsubishi Semiconductor Of America, Inc. Address generator for error control system
US6085288A (en) * 1997-04-14 2000-07-04 International Business Machines Corporation Dual cache directories with respective queue independently executing its content and allowing staggered write operations
US6006311A (en) * 1997-04-14 1999-12-21 Internatinal Business Machines Corporation Dynamic updating of repair mask used for cache defect avoidance
US5943686A (en) * 1997-04-14 1999-08-24 International Business Machines Corporation Multiple cache directories for non-arbitration concurrent accessing of a cache memory
US6023746A (en) * 1997-04-14 2000-02-08 International Business Machines Corporation Dual associative-cache directories allowing simultaneous read operation using two buses with multiplexors, address tags, memory block control signals, single clock cycle operation and error correction
US6061824A (en) * 1998-03-05 2000-05-09 Quantum Corporation Pipelined error correction for minimizing disk re-reading in hard drives
US6115837A (en) * 1998-07-29 2000-09-05 Neomagic Corp. Dual-column syndrome generation for DVD error correction using an embedded DRAM
US6493843B1 (en) * 1999-10-28 2002-12-10 Hewlett-Packard Company Chipkill for a low end server or workstation
JP4489915B2 (ja) * 2000-07-31 2010-06-23 大日本印刷株式会社 暗証コード照合機能をもった携帯型情報処理装置
JP4102313B2 (ja) * 2004-02-05 2008-06-18 株式会社東芝 半導体集積回路装置
US7451380B2 (en) * 2005-03-03 2008-11-11 International Business Machines Corporation Method for implementing enhanced vertical ECC storage in a dynamic random access memory
US7506226B2 (en) * 2006-05-23 2009-03-17 Micron Technology, Inc. System and method for more efficiently using error correction codes to facilitate memory device testing
JP5010271B2 (ja) * 2006-12-27 2012-08-29 富士通株式会社 エラー訂正コード生成方法、およびメモリ制御装置
EP2169555A4 (de) 2007-06-20 2011-01-05 Fujitsu Ltd Cache-steuerung, cache-steuerverfahren und cache-steuerprogramm
JP2010530606A (ja) * 2007-06-21 2010-09-09 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ スタータアンテナを有する高圧放電ランプ
JP5218228B2 (ja) * 2008-04-23 2013-06-26 新東工業株式会社 搬送装置及びブラスト加工装置
US7814300B2 (en) 2008-04-30 2010-10-12 Freescale Semiconductor, Inc. Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access
US8145985B2 (en) 2008-09-05 2012-03-27 Freescale Semiconductor, Inc. Error detection schemes for a unified cache in a data processing system
US8356239B2 (en) 2008-09-05 2013-01-15 Freescale Semiconductor, Inc. Selective cache way mirroring
US8291305B2 (en) 2008-09-05 2012-10-16 Freescale Semiconductor, Inc. Error detection schemes for a cache in a data processing system
US8364896B2 (en) 2008-09-20 2013-01-29 Freescale Semiconductor, Inc. Method and apparatus for configuring a unified cache based on an associated error rate
US8316186B2 (en) 2008-09-20 2012-11-20 Freescale Semiconductor, Inc. Method and apparatus for managing cache reliability based on an associated error rate
US8266498B2 (en) 2009-03-31 2012-09-11 Freescale Semiconductor, Inc. Implementation of multiple error detection schemes for a cache
US8677205B2 (en) * 2011-03-10 2014-03-18 Freescale Semiconductor, Inc. Hierarchical error correction for large memories
US9007350B2 (en) 2011-08-10 2015-04-14 Honeywell International Inc. Redundant display assembly
US8914712B2 (en) 2012-02-27 2014-12-16 Freescale Semiconductor, Inc. Hierarchical error correction
US10437666B2 (en) * 2015-08-06 2019-10-08 Nxp B.V. Integrated circuit device and method for reading data from an SRAM memory
US10223197B2 (en) 2015-08-06 2019-03-05 Nxp B.V. Integrated circuit device and method for applying error correction to SRAM memory
CN108920300A (zh) * 2018-08-02 2018-11-30 郑州云海信息技术有限公司 一种数据操作方法及相关装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2037039B (en) * 1978-12-11 1983-08-17 Honeywell Inf Systems Cache memory system
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
FR2553540B1 (fr) * 1983-10-13 1986-01-03 Centre Nat Rech Scient Dispositif de test aleatoire pour circuits logiques, notamment microprocesseurs
US4586168A (en) * 1983-12-12 1986-04-29 Motorola, Inc. Dual port memory sense amplifier isolation
JPS60133599A (ja) * 1983-12-21 1985-07-16 Nec Corp 半導体メモリ装置
US4661955A (en) * 1985-01-18 1987-04-28 Ibm Corporation Extended error correction for package error correction codes
JPS61214298A (ja) * 1985-03-20 1986-09-24 Toshiba Corp 誤り訂正機能を備えた半導体記憶装置
US4689792A (en) * 1985-09-03 1987-08-25 Texas Instruments Incorporated Self test semiconductor memory with error correction capability
JPH0821238B2 (ja) * 1987-11-12 1996-03-04 三菱電機株式会社 半導体記憶装置
US4920539A (en) * 1988-06-20 1990-04-24 Prime Computer, Inc. Memory error correction system

Also Published As

Publication number Publication date
US5058116A (en) 1991-10-15
EP0418457A2 (de) 1991-03-27
EP0418457B1 (de) 1997-10-01
JPH03108041A (ja) 1991-05-08
DE69031527D1 (de) 1997-11-06
EP0418457A3 (en) 1992-03-18
JPH0531178B2 (de) 1993-05-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee