DE69019822D1 - Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung. - Google Patents

Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung.

Info

Publication number
DE69019822D1
DE69019822D1 DE69019822T DE69019822T DE69019822D1 DE 69019822 D1 DE69019822 D1 DE 69019822D1 DE 69019822 T DE69019822 T DE 69019822T DE 69019822 T DE69019822 T DE 69019822T DE 69019822 D1 DE69019822 D1 DE 69019822D1
Authority
DE
Germany
Prior art keywords
address
checking
word
content
parity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69019822T
Other languages
English (en)
Other versions
DE69019822T2 (de
Inventor
Norbert W Dipl Ing Schumacher
Ingemar Dipl Ing Holm
Gerhard D- Jettingen Di Zilles
Peter Dipl Ing Mannherz
Helmut Dipl Ing Kohler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69019822D1 publication Critical patent/DE69019822D1/de
Publication of DE69019822T2 publication Critical patent/DE69019822T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69019822T 1990-06-27 1990-06-27 Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung. Expired - Fee Related DE69019822T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP90112210A EP0463210B1 (de) 1990-06-27 1990-06-27 Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung

Publications (2)

Publication Number Publication Date
DE69019822D1 true DE69019822D1 (de) 1995-07-06
DE69019822T2 DE69019822T2 (de) 1995-12-14

Family

ID=8204144

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69019822T Expired - Fee Related DE69019822T2 (de) 1990-06-27 1990-06-27 Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung.

Country Status (4)

Country Link
US (1) US5321706A (de)
EP (1) EP0463210B1 (de)
JP (1) JPH0719232B2 (de)
DE (1) DE69019822T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4244275C1 (de) * 1992-12-28 1994-07-21 Ibm Nachprüfung der Datenintegrität bei gepufferter Datenübertragung
SE503589C2 (sv) * 1994-02-10 1996-07-15 Ericsson Telefon Ab L M Förfarande och anordning för övervakning av ett minne
SE503316C2 (sv) * 1994-04-19 1996-05-13 Ericsson Telefon Ab L M Förfarande för övervakning av ett minne samt kretsanordning härför
US5453999A (en) * 1994-04-26 1995-09-26 Unisys Corporation Address verification system using parity for transmitting and receiving circuits
US5486632A (en) * 1994-06-28 1996-01-23 The Dow Chemical Company Group 4 metal diene complexes and addition polymerization catalysts therefrom
US5586253A (en) * 1994-12-15 1996-12-17 Stratus Computer Method and apparatus for validating I/O addresses in a fault-tolerant computer system
US5805799A (en) * 1995-12-01 1998-09-08 Quantum Corporation Data integrity and cross-check code with logical block address
US5841795A (en) * 1996-02-12 1998-11-24 Compaq Computer Corporation Error correction codes
US6003144A (en) * 1997-06-30 1999-12-14 Compaq Computer Corporation Error detection and correction
US6134699A (en) * 1998-01-30 2000-10-17 International Business Machines Corporation Method and apparatus for detecting virtual address parity error for a translation lookaside buffer
US6820213B1 (en) 2000-04-13 2004-11-16 Stratus Technologies Bermuda, Ltd. Fault-tolerant computer system with voter delay buffer
US6687851B1 (en) 2000-04-13 2004-02-03 Stratus Technologies Bermuda Ltd. Method and system for upgrading fault-tolerant systems
US6802022B1 (en) 2000-04-14 2004-10-05 Stratus Technologies Bermuda Ltd. Maintenance of consistent, redundant mass storage images
US6901481B2 (en) 2000-04-14 2005-05-31 Stratus Technologies Bermuda Ltd. Method and apparatus for storing transactional information in persistent memory
US6862689B2 (en) 2001-04-12 2005-03-01 Stratus Technologies Bermuda Ltd. Method and apparatus for managing session information
US6691225B1 (en) 2000-04-14 2004-02-10 Stratus Technologies Bermuda Ltd. Method and apparatus for deterministically booting a computer system having redundant components
US6948010B2 (en) * 2000-12-20 2005-09-20 Stratus Technologies Bermuda Ltd. Method and apparatus for efficiently moving portions of a memory block
US6886171B2 (en) * 2001-02-20 2005-04-26 Stratus Technologies Bermuda Ltd. Caching for I/O virtual address translation and validation using device drivers
US6766413B2 (en) 2001-03-01 2004-07-20 Stratus Technologies Bermuda Ltd. Systems and methods for caching with file-level granularity
US6874102B2 (en) * 2001-03-05 2005-03-29 Stratus Technologies Bermuda Ltd. Coordinated recalibration of high bandwidth memories in a multiprocessor computer
US6928583B2 (en) * 2001-04-11 2005-08-09 Stratus Technologies Bermuda Ltd. Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep
US6996750B2 (en) * 2001-05-31 2006-02-07 Stratus Technologies Bermuda Ltd. Methods and apparatus for computer bus error termination
WO2003043022A2 (de) * 2001-11-12 2003-05-22 Siemens Aktiengesellschaft Speichertest
US8949694B2 (en) 2011-09-23 2015-02-03 International Business Machines Corporation Address error detection
DE102012004780B4 (de) * 2012-03-02 2018-02-08 Fachhochschule Schmalkalden Verfahren und Anordnung zum Schutz von Datengeheimnissen in Speicher
FR2992091B1 (fr) * 2012-06-14 2015-07-03 Commissariat Energie Atomique Procede d'enregistrement de donnees, procede de detection des erreurs d'acces a une memoire et dispositif associe

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL67664A (en) * 1982-01-19 1987-01-30 Tandem Computers Inc Computer memory system with data,address and operation error detection
US4692893A (en) * 1984-12-24 1987-09-08 International Business Machines Corp. Buffer system using parity checking of address counter bit for detection of read/write failures
JPH0799618B2 (ja) * 1986-03-24 1995-10-25 日本電気株式会社 半導体メモリのテスト回路
US4785452A (en) * 1986-04-25 1988-11-15 International Business Machines Corporation Error detection using variable field parity checking
JPH02166700A (ja) * 1988-12-15 1990-06-27 Samsung Electron Co Ltd エラー検査及び訂正装置を内蔵した不揮発性半導体メモリ装置

Also Published As

Publication number Publication date
JPH0719232B2 (ja) 1995-03-06
EP0463210A1 (de) 1992-01-02
DE69019822T2 (de) 1995-12-14
EP0463210B1 (de) 1995-05-31
US5321706A (en) 1994-06-14
JPH0581143A (ja) 1993-04-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee