DE68919636D1 - Ununterbrochene Matrix, deren Plattengrösse programmierbar ist. - Google Patents

Ununterbrochene Matrix, deren Plattengrösse programmierbar ist.

Info

Publication number
DE68919636D1
DE68919636D1 DE68919636T DE68919636T DE68919636D1 DE 68919636 D1 DE68919636 D1 DE 68919636D1 DE 68919636 T DE68919636 T DE 68919636T DE 68919636 T DE68919636 T DE 68919636T DE 68919636 D1 DE68919636 D1 DE 68919636D1
Authority
DE
Germany
Prior art keywords
scribe lines
fixed
bonding pads
wafer
scribe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68919636T
Other languages
English (en)
Other versions
DE68919636T2 (de
Inventor
Piccolo Giovanni Giannella
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Exar Corp
Original Assignee
Exar Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Exar Corp filed Critical Exar Corp
Application granted granted Critical
Publication of DE68919636D1 publication Critical patent/DE68919636D1/de
Publication of DE68919636T2 publication Critical patent/DE68919636T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)
  • Bidet-Like Cleaning Device And Other Flush Toilet Accessories (AREA)
  • Dicing (AREA)
DE68919636T 1988-10-07 1989-10-04 Ununterbrochene Matrix, deren Plattengrösse programmierbar ist. Expired - Fee Related DE68919636T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25509488A 1988-10-07 1988-10-07
US07/277,169 US5016080A (en) 1988-10-07 1988-11-29 Programmable die size continuous array

Publications (2)

Publication Number Publication Date
DE68919636D1 true DE68919636D1 (de) 1995-01-12
DE68919636T2 DE68919636T2 (de) 1995-06-29

Family

ID=26944426

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68919636T Expired - Fee Related DE68919636T2 (de) 1988-10-07 1989-10-04 Ununterbrochene Matrix, deren Plattengrösse programmierbar ist.

Country Status (5)

Country Link
US (1) US5016080A (de)
EP (1) EP0363179B1 (de)
JP (1) JPH02181951A (de)
AT (1) ATE114871T1 (de)
DE (1) DE68919636T2 (de)

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JPH0465859A (ja) * 1990-07-06 1992-03-02 Fujitsu Ltd ウエハ・スケール集積回路および該回路における信号伝播経路形成方法
US5233221A (en) * 1990-10-24 1993-08-03 International Business Machines Corporation Electronic substrate multiple location conductor attachment technology
JP3027864B2 (ja) * 1991-04-02 2000-04-04 富士電機株式会社 半導体装置の製造方法
JPH07302773A (ja) * 1994-05-06 1995-11-14 Texas Instr Japan Ltd 半導体ウエハ及び半導体装置
US5656851A (en) * 1995-05-18 1997-08-12 Elantec Semiconductor, Inc. Semiconductor wafer having slices and limited scribe areas for implementing die
US5861660A (en) * 1995-08-21 1999-01-19 Stmicroelectronics, Inc. Integrated-circuit die suitable for wafer-level testing and method for forming the same
US5767565A (en) * 1996-07-22 1998-06-16 Alliance Semiconductor Corporation Semiconductor devices having cooperative mode option at assembly stage and method thereof
US6289116B1 (en) * 1996-09-27 2001-09-11 Semiconductor Insights, Inc. Computer-assisted design analysis method for extracting device and interconnect information
CA2216900C (en) 1996-10-01 2001-12-04 Semiconductor Insights Inc. Method to extract circuit information
US6250192B1 (en) 1996-11-12 2001-06-26 Micron Technology, Inc. Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
KR19980063858A (ko) * 1996-12-06 1998-10-07 윌리엄비.켐플러 높은 종횡비를 갖는 집적 회로 칩 및 그 제조 방법
ES2313756T3 (es) 1997-10-29 2009-03-01 Genentech, Inc. Usos de polipeptido secretado wisp-1 inducido por wnt-1.
US6242767B1 (en) 1997-11-10 2001-06-05 Lightspeed Semiconductor Corp. Asic routing architecture
US6040632A (en) * 1998-01-14 2000-03-21 Lsi Logic Corporation Multiple sized die
TW367603B (en) * 1998-06-20 1999-08-21 United Microelectronics Corp Electrostatic discharge protection circuit for SRAM
US6403449B1 (en) * 2000-04-28 2002-06-11 Micron Technology, Inc. Method of relieving surface tension on a semiconductor wafer
US6480990B1 (en) * 2000-05-01 2002-11-12 Hewlett-Packard Company Application specific integrated circuit with spaced spare logic gate subgroups and method of fabrication
US7271489B2 (en) * 2003-10-15 2007-09-18 Megica Corporation Post passivation interconnection schemes on top of the IC chips
US6613611B1 (en) 2000-12-22 2003-09-02 Lightspeed Semiconductor Corporation ASIC routing architecture with variable number of custom masks
US6947273B2 (en) * 2001-01-29 2005-09-20 Primarion, Inc. Power, ground, and routing scheme for a microprocessor power regulator
US20030122264A1 (en) * 2001-12-27 2003-07-03 Fong-Long Lin Bond out chip and method for making same
US6885043B2 (en) * 2002-01-18 2005-04-26 Lightspeed Semiconductor Corporation ASIC routing architecture
US6830959B2 (en) * 2002-01-22 2004-12-14 Fairchild Semiconductor Corporation Semiconductor die package with semiconductor die having side electrical connection
TWI268549B (en) * 2002-05-10 2006-12-11 General Semiconductor Inc A surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes and method for using same
US6710414B2 (en) * 2002-05-10 2004-03-23 General Semiconductor, Inc. Surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes
US6953956B2 (en) * 2002-12-18 2005-10-11 Easic Corporation Semiconductor device having borderless logic array and flexible I/O
US7132851B2 (en) * 2003-07-11 2006-11-07 Xilinx, Inc. Columnar floorplan
CA2530796C (en) * 2003-07-11 2010-06-01 Xilinx, Inc. Columnar architecture for pla or fpga
US7129765B2 (en) 2004-04-30 2006-10-31 Xilinx, Inc. Differential clock tree in an integrated circuit
US7337425B2 (en) * 2004-06-04 2008-02-26 Ami Semiconductor, Inc. Structured ASIC device with configurable die size and selectable embedded functions
US7627291B1 (en) * 2005-01-21 2009-12-01 Xilinx, Inc. Integrated circuit having a routing element selectively operable to function as an antenna
US7880278B2 (en) * 2006-05-16 2011-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having stress tuning layer
US7478359B1 (en) 2006-10-02 2009-01-13 Xilinx, Inc. Formation of columnar application specific circuitry using a columnar programmable logic device
KR20090015454A (ko) * 2007-08-08 2009-02-12 삼성전자주식회사 반도체 웨이퍼 및 반도체 소자의 제조 방법
US20100148218A1 (en) * 2008-12-10 2010-06-17 Panasonic Corporation Semiconductor integrated circuit device and method for designing the same
US8701057B2 (en) * 2011-04-11 2014-04-15 Nvidia Corporation Design, layout, and manufacturing techniques for multivariant integrated circuits
US11887976B2 (en) * 2020-10-26 2024-01-30 Mediatek Inc. Land-side silicon capacitor design and semiconductor package using the same

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5568668A (en) * 1978-11-20 1980-05-23 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
US4413271A (en) * 1981-03-30 1983-11-01 Sprague Electric Company Integrated circuit including test portion and method for making
JPS593950A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd ゲ−トアレイチツプ
JPS59107532A (ja) * 1982-12-13 1984-06-21 Nec Corp 半導体装置
JPS59197151A (ja) * 1983-04-22 1984-11-08 Toshiba Corp 半導体集積回路装置
JPS6035532A (ja) * 1983-07-29 1985-02-23 Fujitsu Ltd マスタスライス集積回路装置
JPS6049648A (ja) * 1983-08-30 1985-03-18 Sumitomo Electric Ind Ltd マスタスライスｉｃ
JPS60136332A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置
JPS61272960A (ja) * 1985-05-28 1986-12-03 Yokogawa Electric Corp 半導体装置のトリミング方法
JPH06101521B2 (ja) * 1985-11-13 1994-12-12 日本電気株式会社 半導体集積回路装置
JPS62174941A (ja) * 1986-01-28 1987-07-31 Nec Corp 半導体集積回路
US4835592A (en) * 1986-03-05 1989-05-30 Ixys Corporation Semiconductor wafer with dice having briding metal structure and method of manufacturing same
JPS62229857A (ja) * 1986-03-29 1987-10-08 Toshiba Corp マスタスライス半導体装置
JPS63187648A (ja) * 1987-01-30 1988-08-03 Fuji Xerox Co Ltd ゲ−トアレイ
JPS63291452A (ja) * 1987-05-25 1988-11-29 Nec Corp システム機能を備えた半導体集積回路装置
US4829014A (en) * 1988-05-02 1989-05-09 General Electric Company Screenable power chip mosaics, a method for fabricating large power semiconductor chips

Also Published As

Publication number Publication date
US5016080A (en) 1991-05-14
EP0363179A2 (de) 1990-04-11
ATE114871T1 (de) 1994-12-15
JPH02181951A (ja) 1990-07-16
EP0363179B1 (de) 1994-11-30
DE68919636T2 (de) 1995-06-29
EP0363179A3 (de) 1991-01-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee