TWI268549B - A surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes and method for using same - Google Patents
A surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes and method for using sameInfo
- Publication number
- TWI268549B TWI268549B TW092112471A TW92112471A TWI268549B TW I268549 B TWI268549 B TW I268549B TW 092112471 A TW092112471 A TW 092112471A TW 92112471 A TW92112471 A TW 92112471A TW I268549 B TWI268549 B TW I268549B
- Authority
- TW
- Taiwan
- Prior art keywords
- new
- metal
- mos
- manufacture
- allows
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 title 1
- 239000002184 metal Substances 0.000 abstract 5
- 235000012431 wafers Nutrition 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
A surface geometry for a MOS-gated device is provided that allows device size to be varied in both the x-axis and the y-axis by predetermined increments. The actual device size is set or "programmed" by the metal and pad masks or the contact metal and pad masks. This approach saves both time and expense, since only new contact, metal and pad masks, or new metal and pad mask are required for each new device. Wafers may also be manufactured and stored at an inventory location prior to contact or metal mask, significantly reducing the time required to manufacture new devices. It is also be possible to qualify a family of devices made using this approach without qualifying each device. In addition, the location of the source or the source and gate bonding pads may be easily moved for assembly in a new package or for a new application.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/142,600 US6710414B2 (en) | 2002-05-10 | 2002-05-10 | Surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes |
US10/142,622 US6861337B2 (en) | 2002-05-10 | 2002-05-10 | Method for using a surface geometry for a MOS-gated device in the manufacture of dice having different sizes |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200403730A TW200403730A (en) | 2004-03-01 |
TWI268549B true TWI268549B (en) | 2006-12-11 |
Family
ID=29423049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092112471A TWI268549B (en) | 2002-05-10 | 2003-05-07 | A surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes and method for using same |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1504467A1 (en) |
JP (1) | JP4938236B2 (en) |
CN (2) | CN100530568C (en) |
AU (1) | AU2003241408A1 (en) |
TW (1) | TWI268549B (en) |
WO (1) | WO2003096406A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102004048278B3 (en) * | 2004-10-05 | 2006-06-01 | X-Fab Semiconductor Foundries Ag | Simulation and / or layout method for power transistors designed for different powers |
EP2308096A1 (en) * | 2008-07-28 | 2011-04-13 | Nxp B.V. | Integrated circuit and method for manufacturing an integrated circuit |
JP5742627B2 (en) * | 2011-09-26 | 2015-07-01 | 住友電気工業株式会社 | Semiconductor device and manufacturing method of semiconductor device |
JP5630552B2 (en) * | 2013-10-15 | 2014-11-26 | 富士電機株式会社 | Silicon carbide semiconductor device and manufacturing method thereof |
JP6598037B2 (en) * | 2015-07-01 | 2019-10-30 | パナソニックIpマネジメント株式会社 | Semiconductor device |
US11031343B2 (en) | 2019-06-21 | 2021-06-08 | International Business Machines Corporation | Fins for enhanced die communication |
EP3863065A1 (en) * | 2020-02-04 | 2021-08-11 | Infineon Technologies Austria AG | Semiconductor die and method of manufacturing the same |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5016080A (en) * | 1988-10-07 | 1991-05-14 | Exar Corporation | Programmable die size continuous array |
US5499124A (en) * | 1990-12-31 | 1996-03-12 | Vu; Duy-Phach | Polysilicon transistors formed on an insulation layer which is adjacent to a liquid crystal material |
GB9106720D0 (en) * | 1991-03-28 | 1991-05-15 | Secr Defence | Large area liquid crystal displays |
AU2546897A (en) * | 1996-03-25 | 1997-10-17 | Rainbow Displays, Inc. | Tiled, flat-panel displays with color-correction capability |
JP3276325B2 (en) * | 1996-11-28 | 2002-04-22 | 松下電器産業株式会社 | Semiconductor device |
JP2001352063A (en) * | 2000-06-09 | 2001-12-21 | Sanyo Electric Co Ltd | Insulation gate type semiconductor device |
JP3597762B2 (en) * | 2000-07-24 | 2004-12-08 | 株式会社日立製作所 | Semiconductor integrated circuit and method of manufacturing the same |
-
2003
- 2003-05-07 TW TW092112471A patent/TWI268549B/en active
- 2003-05-09 AU AU2003241408A patent/AU2003241408A1/en not_active Abandoned
- 2003-05-09 EP EP03731142A patent/EP1504467A1/en not_active Withdrawn
- 2003-05-09 CN CNB038106094A patent/CN100530568C/en not_active Expired - Fee Related
- 2003-05-09 CN CN200910150498A patent/CN101697349A/en active Pending
- 2003-05-09 JP JP2004504285A patent/JP4938236B2/en not_active Expired - Fee Related
- 2003-05-09 WO PCT/US2003/014626 patent/WO2003096406A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2003096406A1 (en) | 2003-11-20 |
TW200403730A (en) | 2004-03-01 |
CN1653602A (en) | 2005-08-10 |
EP1504467A1 (en) | 2005-02-09 |
AU2003241408A1 (en) | 2003-11-11 |
JP2005525701A (en) | 2005-08-25 |
CN100530568C (en) | 2009-08-19 |
JP4938236B2 (en) | 2012-05-23 |
CN101697349A (en) | 2010-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SG126711A1 (en) | Manufacturing method of semiconductor device | |
GB2214351B (en) | Method for manufacturing double-diffused metal oxide semiconductor field effect transistor device and the device thereby manufactured | |
AU2003302299A8 (en) | Polishing pad and method for manufacturing semiconductor device | |
SG96201A1 (en) | Flip-chip type semiconductor device and method of manufacturing the same | |
SG118117A1 (en) | Semiconductor device and manufacturing method thereof | |
SG101431A1 (en) | Semiconductor wafer having regular or irregular chip pattern and dicing method for the same | |
DE60238152D1 (en) | Electrode structure for semiconductor device, and manufacturing method and apparatus | |
SG121715A1 (en) | Semiconductor device and method of manufacturing the same | |
TWI348218B (en) | Semiconductor chip and method for manufacturing the same | |
DE60033901D1 (en) | Package for semiconductor device and its manufacturing method | |
TWI350573B (en) | Semiconductor device package and method for manufacturing same | |
HK1048890A1 (en) | Semiconductor device and package, and method of manufacture therefor | |
SG87930A1 (en) | Flip chip type semiconductor and method of manufacturing the same | |
DE102004041514A1 (en) | Solder bump manufacturing method e.g. for use in wafer level package fabrication, involves forming two reinforcing protrusions upwardly extending from chip and mounting substrate, respectively, that are embedded in solder material | |
TW200725709A (en) | Semiconductor apparatus and making method thereof | |
DE60228780D1 (en) | Semiconductor device, associated manufacturing method and liquid jet device | |
EP1441385A4 (en) | Method of forming scribe line on semiconductor wafer, and scribe line forming device | |
AU2002367179A1 (en) | Substrate treating method and production method for semiconductor device | |
GB2393325B (en) | Semiconductor device and manufacturing method thereof | |
TW200737362A (en) | Semiconductor device and method for incorporating a halogen in a dielectric | |
TWI268549B (en) | A surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes and method for using same | |
DE60220762D1 (en) | Semiconductor component and associated manufacturing method | |
DE60210834D1 (en) | Semiconductor component and associated manufacturing method | |
EP1424409A4 (en) | Semiconductor wafer and its manufacturing method | |
EP1437765A4 (en) | Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor |