TW200403730A - A surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes and method for using same - Google Patents

A surface geometry for a MOS-gated device that allows the manufacture of dice having different sizes and method for using same Download PDF

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TW200403730A
TW200403730A TW092112471A TW92112471A TW200403730A TW 200403730 A TW200403730 A TW 200403730A TW 092112471 A TW092112471 A TW 092112471A TW 92112471 A TW92112471 A TW 92112471A TW 200403730 A TW200403730 A TW 200403730A
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Richard A Blanchard
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Gen Semiconductor Inc
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/402—Field plates
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Abstract

A surface geometry for a MOS-gated device is provided that allows device size to be varied in both the x-axis and the y-axis by predetermined increments. The actual device size is set or "programmed" by the metal and pad masks or the contact metal and pad masks. This approach saves both time and expense, since only new contact, metal and pad masks, or new metal and pad mask are required for each new device. Wafers may also be manufactured and stored at an inventory location prior to contact or metal mask, significantly reducing the time required to manufacture new devices. It is also be possible to qualify a family of devices made using this approach without qualifying each device. In addition, the location of the source or the source and gate bonding pads may be easily moved for assembly in a new package or for a new application.

Description

200403730 (1) 玖、發明說明 【發明所屬之技術領域】 本發明大體上關於MOS閘裝置，及其製造方法。 【先前技術】 已開發大量表面幾何圖形，俾用以製造MOS閘裝置。 該些表面幾何圖形或「佈局」包括叉合結構，以及重複或 「蜂巢」結構，包括以HEXFET®MOSFET (金屬氧化物半 導體場效電晶體）爲例之知名的六角幾何圖形。該些被開 發之不同的表面幾何圖形，可完美發揮裝置的特性，例如 線上阻抗與加固。對一特定幾何圖形及電壓而言，裝置的 線上阻抗與活動的裝置區成反比。使用現有表面幾何圖形 設計具有所需線上阻抗的新裝置，僅需計算現有裝置的線 上阻抗乘以其活動區的結果。依據此資訊，決定了新裝置 的活動區，墊及終端添加了頂蓋，並可製造具所需線上阻 抗的裝置。 然而，爲每一不同線上阻抗値或每一不同尺寸的MO S 閘裝置製造新遮罩組的傳統方法是不受歡迎的，其中導致 產生大量的裝置遮罩組，而渠等裝置間的線上阻抗與活動 區均不相同。再者，每一件該些裝置在送交客戶之前，必 須個別檢定。傳統裝置亦不提供簡單機件供閘極與源極墊 移動，俾利特定終端使用。 因而在本技藝中需要一種製造MOS閘裝置的方法，其 僅需製造一組遮罩，便可使用相同遮罩，便可製造具不同 -4- (2) 200403730 尺寸與不同線上阻抗的Μ 0 S閘裝置。在本技 種製造MOS閘裝置的方法，如此便可檢定同 需檢定同批中的每一特定裝置。最後，在本 種Μ Ο S閘裝置的表面設計，使閘極及源極墊 置內移動，以利特定終端使用，不需大量 業。本文所揭露的方法與裝置，可滿足渠等 【發明內容】 本文揭露MOS閘裝置的模組表面幾何圖 些表面幾何圖形製造MOS閘裝置的方法。該 何圖形使得裝置的尺寸在X軸與Υ軸可經由 而有所改變。 在本文所揭露的裝置及方法的若干實施 裝置尺寸是由接點、金屬及墊遮罩設定或「 在其他實施例中，裝置尺寸僅由金屬及墊遮 每一新裝置僅需新接點、金屬及墊遮罩，或 罩，所以此方法可節省時間及花費。此外， 置中的晶圓，在接點或金屬遮罩之前可被製 貨位置’因而在知悉裝置規格前，便可執行 程序。此接著明顯地降低製造新裝置所需的 使用此方法亦可檢定同批的裝置，不需 裝置。此外，源極與閘極結合墊的位置可輕 建新的封包，或進行新的應用。因此，此方 新遮罩組，因應每一新裝置所需，提供了傳 藝中亦需要一 批的裝置，不 技藝中需要一 可輕易地在裝 的重複工程作 及其他需求。 形，及使用該 些模組表面幾 預設的增量， 例中，實際的 程控」，同時 罩程控。由於 新金屬及墊遮 將用於該些裝 造並存放於存 大部分的製造 時間。 檢定每一特定 易地移動以組 法製造完整的 統方法的替代 -5- (3) (3)200403730 々巳巳 进擇。 在一觀點中，本文揭露一種製造Μ 0 S閘裝置的方法。 依據此方法，提供複數個獨立的晶塊，各具有至少一源極 區，及至少一本體區。每一晶塊亦將典型地具有多個閘極 接點區分佈其上。該複數個晶塊納入一陣列，以形成一 MOS閘裝置，較佳地，各晶塊的尺寸基本上相同。亦較佳 的是，晶塊的形狀爲矩形或方形。一閘極金屬化層可能是 例如一系列個別的金屬軌跡，該層分佈於至少部份的該陣 列上，如此便與該陣列中閘極接點區電氣接觸。源極及金 屬化層分佈於至少部份的該陣列上，如此便與晶塊的源極 及本體區電氣接觸。終端金屬化層亦典型地分佈於形成裝 置外緣的晶塊上，使其典型地與外緣晶塊的閘極接點區， 及源極及本體接點區電氣接觸。 在另一觀點中，本文揭露一種Μ Ο S閘裝置，其包括個 別晶塊的陣列，其中該陣列的每一晶塊具有源極區、本體 區及閘極接點區。其中源極及本體金屬化層與該陣列中至 少二晶塊的源極及本體區電氣接觸，而閘極金屬化層則與 該陣列中至少二晶塊的閘極接點電氣接觸。較佳地，陣列 中每一晶塊具有四個閘極接點區，其中至少兩個與分佈於 陣列內側的閘極金屬化層接觸。該些晶塊典型地分佈於陣 列中，使得鄰近晶塊間存有間隙，而源極及本體金屬化層 則較佳地延伸跨越該間隙。閘極金屬化層及源極及本體金 屬化層將典型地彼此電氣絕緣，藉以維持彼此間的實體間 隙或空間。陣列中晶塊具有溝形或平面結構。 -6 - (4) (4)200403730 在又另一觀點中，本文所提供的Μ O S閘裝置，其包括 個別晶塊的陣列。該陣列包括沿陣列外側分佈的第一複數 個晶塊，及分佈於陣列內側的第二複數個晶塊。每一第一 及第二複數個晶塊，具有源極及本體區，及閘極接點區。 裝置進一步包括源極及本體金屬化層，其與第一及第二複 數個晶塊的源極及本體區電氣接觸；及終端金屬化層，其 與該第一及第二複數個晶塊中至少一源極及本體區，及至 少一閘極接點區電氣接觸。 本文所揭露之方法與裝置的該些及其他觀點，將於以 下進一步詳細說明。 【實施方式】 本文揭露Μ Ο S閘裝置的模組佈局幾何圖形，其可經由 預設的增量，使得裝置的尺寸在X軸與γ軸均可改變，並 揭露使用Μ Ο S閘裝置製造中該些佈局幾何圖形的方法，該 裝置經由單一遮罩組，具有可變尺寸與線上阻抗（即該方 法於製造每一新裝置時，僅需新接點、金屬及墊遮罩，或 新金屬及墊遮罩）。依據本文所揭露之方法，可並列配置 複數個基本相同的晶塊，以獲取具所需尺寸及線上阻抗的 裝置形成陣列。 在下列參照附圖的討論中，以相同的編號代表相同的 元件。 圖1中描繪依據本文所揭露原理而設計的一般裝置佈 局。顯不相同晶塊1 3的7 X 9陣列1 1。由於在完成的裝置 >7- (5) (5)200403730 中，外緣晶塊1 5跨越標線1 7，所以實際裝置包括6 χ 8陣列 的晶塊（參閱圖1 〇之兀件7 4，可見7 X 9陣列中的標線 17 )。因此，每一外緣晶塊實際上由完整裝置中的半個晶 塊組成。選擇基本晶塊的尺寸’以便晶塊的外緣形成裝置 的終端，並延伸跨越標線，亦形成在垂直與水平方向鄰近 之四個晶粒（未顯示）的邊緣終端，以及在角落鄰近的另 四個晶粒。每一晶塊較佳的爲方形或矩形，其中任兩個晶 塊較佳地具有相同尺寸。亦較佳的是，每一晶塊的長度與 寬度較佳地相同（即該晶塊較佳的爲方形）。 圖2-3顯示晶塊的兩種代表類型，可用於實踐本文所 揭露的方法。在圖2所描繪的晶塊2 1 a中，當沿線1 1 -1〗或 軸3 4檢視時，晶塊內部的源極及本體區3 1 a的排列是相同 的（即圖2中的晶塊是對稱的）。溝Μ Ο S閘裝置的截面描 繪於圖1 1中。 相較之下，圖3所描繪的晶塊2 1 b中，源極及本體區 3 lb的排列並非對稱。尤其是，在圖3所描繪的晶塊中，當 沿線12-12檢視時（溝MOS閘裝置的截面描繪於圖12 中）’晶塊內部的源極及本體區3 1 b的排列，不同於當沿 軸3 6檢視時，晶塊內部的源極及本體區的排列（後者的截 面圖與圖2中沿線11 -1 1檢視之晶塊2 1 a的截面圖相同）。 圖2中內部源極及本體區的幾何圖形顯示爲方形，但 亦可爲矩形、多邊形（包括例如六角形或八角形）、圓 $ '或可爲由直線及/或曲線合成所定義的形狀。同樣 ί也’圖3中內部源極及本體區的幾何圖形顯示爲矩形，其 -8- (6) (6)200403730 亦可由大量的可能性中加以選擇。雖然圖2及圖3之外部源 極及本體區的幾何圖形（分別爲元件3 3 a及3 3 b )顯示爲一 邊開口的方形’但它們的形狀亦可由大量的可能性中加以 選擇。在一種可能的替代中，圖2及圖3的三個外部突出閘 極區（分別爲元件3 5 a及3 5 b )被移走，餘下閘極接點墊 3 7a與3 7b之間具直線側的閘極。 圖4 - 6描繪三個特定金屬化層的設計，其可用於本文 所揭露裝置中，晶塊陣列4 3 a、4 3 b及4 3 c內部，四個相同 電氣主動晶塊41a-d之角落的連接。當然，熟悉本技藝之 人士應理解，大量的其他內部金屬化類型亦是可能的。陣 列中每一晶塊配置至少一暴露的多矽物部分，作爲閘極接 點墊4 5 (其餘的多矽物典型地由電介質層覆蓋）。 在特定陣列中顯示，晶塊沿每一軸配置，相聚間隙4 6 或溝。陣列中至少若干晶塊的閘極接點墊直接或間接地， 被導入與陣列中其他晶塊上的一或多個閘極接點墊電氣接 觸。因此，在圖4所描繪的陣列中，第一 4 1 a及第二4 1 b晶 塊上的閘極接點墊，被「狗骨」形閘極金屬化層47a導入 彼此電氣接觸，而第三4 1 c及第四4 1 d晶塊上的閘極接點 墊，則以相同的方式電氣接觸。在圖5中，陣列中第一 4 1 a 及第二4 1 b晶塊上的閘極接點墊，被縱向延伸的閘極金屬 化層47b導入彼此電氣接觸，而第三41c及第四41d晶塊上 的閘極接點墊，則以相同的方式電氣接觸。在圖6中，陣 列中第一 41a、第二41b、第三41c及第四41 d晶塊上的閘極 接點墊，被Η形閘極金屬化層47c導入彼此電氣接觸。 (7) (7)200403730 在圖4 - 6所描繪的每一內部金屬化實施例中，閘極金 屬化層4 7 a - c與源極及本體金屬化層5丨電氣絕緣。較佳 地，由於從製造的觀點來看，此設計一般而言極具成本效 益’其係在兩金屬化層間分離空間或溝5 3而完成，所以兩 金屬化層基本上共面。然而，其他實施例亦是可能的，其 中兩金屬化層分佈於堆疊設計中的不同層，其間配置電介 質材料，以確保彼此仍爲電氣絕緣。在此實施例中，例如 閘極接點墊可與第一薄金屬化層連接，同時源極及本體區 可與第二較厚的金屬化層連接。 圖7 - 9描繪跨越晶粒外部角落四個相同晶塊之可能金 屬化結構的特定範例。當然，熟悉本技藝之人士應理解， 大量的其他金屬化結構亦是可能的。在圖7所描繪的層6 1 中，終端金屬化層7 0 a延伸跨越外部晶塊6 5、6 6及6 7，將 源極及本體區導引與該些晶塊的閘極接點墊電氣接觸。源 極及本體金屬化層7 1 a延伸跨越內部晶塊6 8的部分。閘極 金屬化層63 a延伸跨越內部晶塊68，其包括閘極接點墊 6 9 a ° 除了終端金屬化層7 0 b及源極及本體金屬化層7 1 b較接 近，且內部晶塊6 8的閘極接點墊爲電氣絕緣外，圖8之陣 列6 1 b與圖7中陣列相似。圖9之陣列6 1 c與圖8中陣列的不 同處，主要在於終端金屬化層7 0 c與源極及本體金屬化層 6 9 c的形狀。再提一次，內部晶塊6 8的閘極接點墊7 2爲電 氣絕緣。 在製造圖1 -9所描繪之類型的陣列中，有所助益之晶 -10- (8) (8)200403730 塊設計背後的若干主要特性及考量，如次： 1 ·較佳地選取晶塊的尺寸，以便每一晶塊邊緣的長度 及寬度，恰爲標線寬度加上晶塊每側所出現裝置之邊緣終 端寬度，所需的尺寸（可替代地，晶塊邊緣的長度及寬度 可選取爲標線尺寸加上晶塊每側所出現裝置之邊緣終端寬 度，並乘上一整數）。 2 .爲減少源極及本體金屬化層所提供的阻抗，該層較 佳地延伸至所有源極及本體接點，並較佳地具有最大的可 能寬度。 3 ·每一晶塊的閘極導體，較佳地具有足夠接點，以便 於金屬化時，提供可接受的低阻抗予整個閘極。 4 ·位於邊緣之晶塊的閘極導體與源極及本體區，當以 金屬相連時，較佳地提供可接受的邊緣終端。 5 ·源極墊較佳地利用「主動區上連結」之已知技術， 位於一或多個晶塊或晶塊部分之上。使用該組合技術，一 或多條線鍵便附著於源極及本體金屬化層，直接位於源極 及本體與閘極區之上。使用主動區上連結，增加了具源極 及本體區的晶片區，提昇了使用，並消除了本發明文中專 用「源極連結墊」的需求。 6 .閘極墊較佳地不與晶塊的源極及本體區連接，而在 任何晶塊或晶塊組上形成。 圖10描繪圖1中垂直DMOS裝置的詳細佈局。雖然可使 用任一尺寸的陣列製造垂直DMOS，但圖10中所示特定陣 列71爲晶塊73的7 X 9陣列。應注意的是，當然，每一邊的 -11 - (9) (9)200403730 每一晶塊的1 /2屬於鄰近裝置，所以圖1 0中所示7 χ 9陣 列，實際上的有效尺寸僅爲6 X 8晶塊。在所示的特定陣列 中，閘極墊7 5位於裝置的底部中央，而源極墊7 7則位於裝 置中心。沿每軸之晶塊奇數或偶數數量的選擇，影響源極 及本體墊的位置、閘極墊的位置、及裝置的對稱性。 本文所說明之晶塊，可許用多個源極墊及/或閘極 墊，供各連結現附著。此特性使得相當大量裝置的製造， 不會明顯增加源極及本體金屬化中或閘極導體中的串連阻 抗。 到目前爲止，已說明之晶塊具有相同的長度與寬度。 然而，在裝置中或本文所說明的方法中，亦可能使用不同 的長度與寬度。然而，爲求最佳佈局效率，若晶塊的長度 與寬度不相等，較佳地，晶塊的最長尺寸爲最短尺寸的整 數倍。 圖2及3中所示晶塊，可使用溝技術及平面技術製造。 若使用溝技術，則僅形成閘極接點3 7 a及3 7 b的多晶矽區 域’位於晶圓的表面上。 圖1 1及1 2描繪圖2及3中所示晶塊的細節，其具有溝 D M 0 S結構。圖2沿線1 1 - 1 1檢視之格的截面圖描繪於圖1 1 中。此截面圖與圖2中沿軸3 4檢視之截面圖相同（即晶塊 是對稱的），並與圖3中沿軸3 6檢視之截面圖相同。圖3沿 線1 2 -1 2檢視之截面圖描繪於圖1 2中，其不同於沿軸3 6檢 視之截面圖（即晶塊是非對稱的）。後者之截面圖與圖1 1 中所丨田繪之截面圖相同。 -12- (10) (10)200403730 參閱圖11及圖12，其中所描繪之裝置包括N +基底91 及外延層9 3。一連串的溝9 5形成於外延層中。每一溝塡注 摻雜多矽物9 7，並包括閘極氧化物層9 9。每溝以雙擴散源 極及本體區1 〇 1爲界，後者包括源極1 〇 3、淺擴散P型區1 〇 4 及深擴散P +區1 〇 5。源極及本體金屬化層1 〇 7呈現於頂 面，與源極及本體區1 〇 1連接。 如表1中所示，晶粒尺寸可做成具有多列及行的個別 晶塊，並具有單一晶塊做爲閘極墊。由製造的觀點看來， 鑑於產生的外觀比例，若干晶粒尺寸可能不甚討喜。對此 範例而言，具有大於3 : 1之外觀比例的裝置，可能不易製 造。除了表1中所列，以及大於表1中所列的晶粒尺寸，亦 可獲得其他的晶粒尺寸。對於個別陣列的尺寸並無特定上 限（每一陣列均具有單一晶塊做爲閘極墊），但若晶粒尺 寸成長太大，則可能有製造的顧慮。具有一閘極墊之個別 陣列的最小實際尺寸，是由相對於單一閘極墊陣列之主動 陣列的數量決定。若個別陣列尺寸小於2 X 3晶塊，則無主 動晶塊可供處理。在2 X 3的個別陣列尺寸，源極及主體晶 塊區與閘極墊晶塊區的比例是1 : 1，此對於許多應用而言 過小而無法實踐。 (11)200403730 表1:不 同尺寸裝置的晶塊設計 內部晶 內部陣 源極及主體 閘極晶 水平方向 垂直方向 內部晶塊數與 塊數量 列的尺寸 晶塊的數量 塊數量 的晶塊總數 的晶塊總數 總晶塊數的比例 2 1x2 1 1 2 3 2:6 3 1x3 2 1 2 4 3:8 4 2x2 3 1 3 3 4:9 6 2x3 5 1 3 4 6:12 8 2x4 7 1 3 5 8:15 9 3x3 8 1 4 4 9:16 10 2x5 9 1 3 6 10:18 12 3x4 11 1 4 5 12:20 15 3x5 14 1 4 6 15:24 18 3x6 17 1 4 7 18:28 20 4x5 19 1 5 6 20:30 25 5x5 24 1 6 6 25:36 30 5x6 29 1 6 7 30:42 35 5x7 34 1 6 8 35:48 40 5x8 39 1 6 9 40:54 49 7x7 48 1 8 8 49:64 64 8x8 63 1 9 9 64:81 81 9x9 80 1 10 10 81:100 100 10x 10 99 1 11 11 100:121 (12) (12)200403730 使用先前所揭露之晶塊製造的裝置，產生每一新裝置 時，需要接點遮罩、金屬遮罩與墊遮罩。透由在次陣列中 以固定間隔包含專用閘極墊遮罩，每一新裝置之個別接點 遮罩的需求可予已省略。次陣列中專用閘極墊遮罩的位置 可.予已選擇，以便於每一晶粒提供一或多個閘極墊。在若 干實施例中，專用閘極墊晶塊具有與主動晶塊相同的多石夕 層幾何圖形，並具有主體摻雜物，但目前無源極摻雜物， 未與主體區電氣接觸。 在其他實施例中，專用閘極墊晶塊具有持續的多矽層 幾何圖形，僅外緣與主動晶塊的幾何圖形匹配。主體摻雜 物目前持續在多矽物之下，與源極及主體終端電氣浮動或 電氣接觸。各式其他的多矽幾何圖形及摻雜物位置，可在 不影響晶塊之電氣性能，或不顯著增加裝置線上阻抗下， 用於達成與閘極的電氣接觸。 閘極墊晶塊間在水平與垂直方向配置著奇數或偶數數 量的主動晶塊。若於每一軸在閘極墊晶塊間選擇奇數，便 將獲得較大的對稱性。於每一方向的閘極墊晶塊間之主動 晶塊的確實數量，決定所允許之相同晶粒的晶粒尺寸。在 圖1 3之裝置1 1 1中，例如於水平方向在閘極墊晶塊1 1 3 a間 有5個主動晶塊1 1 5 a，在垂直方向有7個主動晶塊。在整個 次陣列1 17a中，計算列數與行數，共有6行8列。 可使用任一數量的次陣列來設計裝置，其中每一均具 有一閘極墊晶塊。在圖1 3 -1 5所顯示的範例中，可獲得三 個代表性的晶粒尺寸’顯示爲5 X 7次陣列，連同三種可能 -15- (13) 200403730 的次陣列安排1 1 7 a、1 1 7 b及1 1 7 c。因而，圖1 3描繪包括次 陣列1 1 7 a之3 X 3安排的裝置。圖1 4描繪方位1 X 2次陣列 1 1 9，圖1 5描繪方位2 X 3次陣列1 2 1。表2列出若干由圖1 5 所示次陣列所組成的其他可能裝置。 -16- (14)200403730 表2 :具有專用閘極墊並包含6x8晶塊之次陣列的安排 次陣列數量 次陣列的方位 水平方向 的晶塊總數 垂直方向 的晶塊總數 主動晶塊對 總晶塊數量比 外觀比 1 1x1 6 8 34:48 3:4 2 1x2 6 16 73:96 3:8 2 2x1 12 8 75:96 3:2 3 1x3 6 24 112:144 1:4 3 3x1 18 8 116:144 9:4 4 1x4 6 32 151:192 3:16 4 2x2 12 16 161:192 3:4 4 4x1 24 8 157:192 3:1 5 1x5 6 40 190:240 3:20 5 5x1 30 8 198:240 15:4 6 1x6 6 48 229:288 1:6 6 2x3 12 24 247:288 1:2 6 3x2 18 16 249:288 9:8 6 6x1 36 8 239:288 9:2 7 1x7 6 56 268:336 3:28 7 7x1 42 8 280:336 21:4 8 1x8 6 64 307:384 3:32 8 2x4 12 32 333:384 3:8 8 4x2 24 16 337:384 3:2 8 8x1 48 8 321:384 6:1 9 1x9 6 72 346:432 1:12 9 3x3 18 24 382:432 3:4 9 9x1 54 8 362:432 27:4200403730 (1) (ii) Description of the invention [Technical field to which the invention belongs] The present invention generally relates to a MOS gate device and a manufacturing method thereof. [Previous Technology] A large number of surface geometries have been developed for manufacturing MOS gate devices. These surface geometries or "layouts" include bifurcated structures and repeating or "honeycomb" structures, including well-known hexagonal geometries such as HEXFET® MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). These different surface geometries were developed to make perfect use of device characteristics such as on-line impedance and reinforcement. For a particular geometry and voltage, the on-line impedance of the device is inversely proportional to the active device area. Using existing surface geometry to design a new device with the required on-line impedance, simply calculate the result of multiplying the on-line impedance of the existing device by its active area. Based on this information, the active area of the new device is determined, and the cover is added to the pad and terminal, and a device with the required online resistance can be manufactured. However, the traditional method of manufacturing a new mask set for each different line impedance 値 or each different size of the MOS gate device is not welcome, which results in a large number of device mask sets, and the lines between devices such as channels Both impedance and active area are different. Furthermore, each of these devices must be individually tested before being sent to the customer. Traditional devices also do not provide simple mechanisms for moving the gate and source pads, which is beneficial for specific terminals. Therefore, in this technique, a method for manufacturing a MOS gate device is needed. It only needs to manufacture a set of masks, and the same mask can be used to manufacture M0 with different -4- (2) 200403730 sizes and different line impedances. S-gate device. In this technique, a method for manufacturing a MOS gate device can be used to test each specific device in the same batch. Finally, in the surface design of this MOS gate device, the gate and source pads are moved to facilitate the use of a specific end, without the need for a large amount of industry. The method and device disclosed in this article can meet the requirements of the channel and the like. [Summary] This article discloses the surface geometry of the module of the MOS gate device. What graphics make the size of the device changeable between the X and Y axes. Several implementations of the devices and methods disclosed herein are set by contact, metal, and pad masks or "in other embodiments, the device size is only covered by metal and pads. Each new device requires only new contacts, Metal and pad masks, or hoods, so this method saves time and money. In addition, the placed wafer can be placed in the manufacturing position before the contact or metal mask ', so it can be performed before the device specifications are known Procedure. This then significantly reduces the need to make new devices. Using this method can also verify the same batch of devices without devices. In addition, the location of the source and gate pads can be used to lightly build new packages or perform new applications. . Therefore, the new mask set of this side, in response to the needs of each new device, provides a batch of devices that are also needed in the process of transmission, and does not require a repeated project and other requirements that can be easily installed. Use a few preset increments on the surface of these modules, for example, the actual program control ", while covering the program control. As new metal and pads will be used for these fabrications and stored for most of the fabrication time. Test the alternatives of each specific ex-situ move to create a complete system by means of group method. -5- (3) (3) 200403730 进 Alternatives. In one aspect, a method for manufacturing an M 0 S gate device is disclosed herein. According to this method, a plurality of independent crystal blocks are provided, each having at least one source region and at least one body region. Each ingot will also typically have a plurality of gate contact regions distributed thereon. The plurality of crystal blocks are incorporated into an array to form a MOS gate device. Preferably, the size of each crystal block is substantially the same. It is also preferred that the shape of the crystal block is rectangular or square. A gate metallization layer may be, for example, a series of individual metal tracks that are distributed over at least a portion of the array so as to make electrical contact with the gate contact areas in the array. The source electrode and the metallization layer are distributed on at least part of the array, so as to make electrical contact with the source and body regions of the crystal block. The terminal metallization layer is also typically distributed on the crystal block forming the outer edge of the device, so that it is typically in electrical contact with the gate contact region, the source electrode, and the body contact region of the outer crystal block. In another aspect, this document discloses an MOS gate device including an array of individual crystal blocks, wherein each crystal block of the array has a source region, a body region, and a gate contact region. The source and body metallization layers are in electrical contact with the source and body regions of at least two crystal blocks in the array, and the gate metallization layer is in electrical contact with the gate contacts of at least two crystal blocks in the array. Preferably, each crystal block in the array has four gate contact regions, at least two of which are in contact with a gate metallization layer distributed inside the array. The crystal blocks are typically distributed in an array so that there is a gap between adjacent crystal blocks, and the source and bulk metallization layers preferably extend across the gap. The gate metallization layer and the source and bulk metallization layers will typically be electrically insulated from each other, thereby maintaining a physical gap or space between each other. The crystal blocks in the array have a trench or planar structure. -6-(4) (4) 200403730 In yet another aspect, the MOS gate device provided herein includes an array of individual crystal blocks. The array includes a first plurality of crystal blocks distributed along the outside of the array, and a second plurality of crystal blocks distributed inside the array. Each of the first and second plurality of crystal blocks has a source electrode and a body region, and a gate contact region. The device further includes a source electrode and a bulk metallization layer, which are in electrical contact with the source and body regions of the first and second plurality of crystal blocks; and a terminal metallization layer, which is in contact with the first and second plurality of crystal blocks. At least one source and body region and at least one gate contact region are in electrical contact. These and other aspects of the methods and devices disclosed herein will be described in further detail below. [Embodiment] This article discloses the module layout geometry of the MOS gate device, which can be changed in the X-axis and γ axis through preset increments, and discloses the use of the MEMS gate device. In these methods of layout geometry, the device passes a single mask set with variable size and on-line impedance (that is, the method requires only new contacts, metal and pad masks when manufacturing each new device, or new Metal and pad masks). According to the method disclosed herein, a plurality of substantially the same crystal blocks can be arranged in parallel to obtain an array of devices having the required size and on-line impedance. In the following discussion with reference to the drawings, the same elements are denoted by the same reference numerals. Figure 1 depicts a general device layout designed in accordance with the principles disclosed herein. 7 x 9 arrays 1 1 which are different from the crystal blocks 1 3. Because in the completed device> 7- (5) (5) 200403730, the outer edge crystal block 15 crosses the reticle 17, so the actual device includes a 6 x 8 array of crystal blocks (see Fig. 10, element 7). 4. You can see the marking 17 in the 7 X 9 array). Therefore, each outer crystal block is actually composed of half of the crystal blocks in the complete device. The size of the basic ingot is selected so that the outer edge of the ingot forms the end of the device and extends across the reticle. It also forms the end of the edges of four grains (not shown) adjacent to each other vertically and horizontally, and adjacent corners. Another four grains. Each ingot is preferably square or rectangular, and any two ingots preferably have the same size. It is also preferred that the length and width of each ingot are preferably the same (that is, the ingot is preferably square). Figure 2-3 shows two representative types of ingots that can be used to practice the methods disclosed in this article. In the crystal block 2 1 a depicted in FIG. 2, when viewed along the line 1 1 -1 or the axis 34, the arrangement of the source and the body region 3 1 a inside the crystal block are the same (that is, in FIG. 2 The ingot is symmetrical). The cross-section of the trench MOS gate device is depicted in FIG. In comparison, in the crystal block 2 1 b depicted in FIG. 3, the arrangement of the source and the body region 3 lb is not symmetrical. In particular, in the crystal block depicted in FIG. 3, when viewed along line 12-12 (the cross section of the trench MOS gate device is depicted in FIG. 12), the arrangement of the source and the body region 3 1 b inside the crystal block is different. When viewed along axis 36, the arrangement of the source and body regions inside the crystal block (the cross-sectional view of the latter is the same as the cross-sectional view of crystal block 2 1 a viewed along line 11-1 1 in Figure 2). The geometry of the internal source and body regions in FIG. 2 is shown as a square, but it can also be a rectangle, a polygon (including, for example, a hexagon or an octagon), a circle, or a shape defined by line and / or curve synthesis . Similarly, the geometry of the internal source and body regions in Figure 3 is shown as a rectangle, and its -8- (6) (6) 200403730 can also be selected from a large number of possibilities. Although the geometry of the external source and body regions of Figures 2 and 3 (elements 3 3a and 3 3 b, respectively) are shown as squares with open sides, their shapes can also be selected from a large number of possibilities. In a possible alternative, the three externally protruding gate regions (elements 3 5 a and 3 5 b respectively) of FIGS. 2 and 3 are removed, and the remaining gate contact pads 3 7a and 37b have Gate on straight side. Figures 4-6 depict the design of three specific metallization layers, which can be used in the device disclosed herein. Inside the crystal block arrays 4 3 a, 4 3 b, and 4 3 c, four of the same electrically active crystal blocks 41a-d Corner connection. Of course, those skilled in the art should understand that a large number of other internal metallization types are also possible. Each crystal block in the array is provided with at least one exposed polysilicon portion as a gate contact pad 4 5 (the remaining polysilicon is typically covered by a dielectric layer). It is shown in a specific array that the ingots are arranged along each axis, with a gap of 4 6 or grooves. The gate contact pads of at least several crystal blocks in the array are directly or indirectly introduced into electrical contact with one or more gate contact pads on other crystal blocks in the array. Therefore, in the array depicted in FIG. 4, the gate contact pads on the first 4 1 a and the second 4 1 b crystal blocks are brought into electrical contact with each other by the “dog-bone” shaped gate metallization layer 47a, and The gate contact pads on the third 4 1 c and fourth 4 1 d crystal blocks are electrically contacted in the same manner. In FIG. 5, the gate contact pads on the first 4 1 a and the second 4 1 b crystal blocks in the array are brought into electrical contact with each other by the longitudinally extending gate metallization layer 47 b, and the third 41c and the fourth The gate contact pads on the 41d crystal block are electrically contacted in the same way. In FIG. 6, the gate contact pads on the first 41a, the second 41b, the third 41c, and the fourth 41d in the array are brought into electrical contact with each other by the gate-shaped metallization layer 47c. (7) (7) 200403730 In each of the internal metallization embodiments depicted in Figures 4-6, the gate metallization layers 4 7 a-c are electrically insulated from the source and bulk metallization layers 5 丨. Preferably, since the design is generally very cost effective from a manufacturing point of view, it is accomplished by separating spaces or trenches 53 between the two metallization layers, so the two metallization layers are substantially coplanar. However, other embodiments are also possible, in which two metallization layers are distributed in different layers in a stacked design, and a dielectric material is disposed therebetween to ensure that they are still electrically insulated from each other. In this embodiment, for example, the gate contact pads can be connected to the first thin metallization layer, while the source and body regions can be connected to the second thicker metallization layer. Figures 7-9 depict specific examples of possible metallization structures across four identical ingots across the outer corners of the die. Of course, those skilled in the art should understand that a large number of other metallized structures are also possible. In the layer 6 1 depicted in FIG. 7, the terminal metallization layer 7 0 a extends across the external crystal blocks 6 5, 6 6 and 67 and guides the source and body regions to the gate contacts of the crystal blocks. Pad electrical contact. The source and bulk metallization layer 7 1 a extends across a portion of the inner crystal block 68. The gate metallization layer 63a extends across the inner crystal block 68, which includes the gate contact pads 6 9 a ° except that the terminal metallization layer 7 0 b and the source and bulk metallization layers 7 1 b are closer, and The gate contact pads of block 68 are electrically insulated. The array 6 1 b of FIG. 8 is similar to the array of FIG. 7. The difference between the array 6 1 c in FIG. 9 and the array in FIG. 8 mainly lies in the shapes of the terminal metallization layer 70 c and the source and bulk metallization layers 69 c. Again, the gate contact pads 72 of the internal crystal block 68 are electrically insulated. In the manufacture of the types of arrays depicted in Figures 1-9, the crystals are helpful. -10- (8) (8) 200403730 Several main characteristics and considerations behind the block design, such as: 1 · Better selection of crystals The size of the block, so that the length and width of the edge of each crystal block is exactly the width of the ruled line plus the edge terminal width of the device appearing on each side of the crystal block, and the required size (alternatively, the length and width of the edge of the crystal block It can be selected as the size of the marked line plus the terminal width of the edge of the device appearing on each side of the crystal block, and multiplied by an integer). 2. In order to reduce the impedance provided by the source and body metallization layers, this layer preferably extends to all source and body contacts and preferably has the largest possible width. 3. The gate conductor of each crystal block preferably has enough contacts to provide an acceptable low impedance to the entire gate during metallization. 4 · The gate conductor, source and body area of the crystal block located at the edge, when connected by metal, preferably provide an acceptable edge termination. 5. The source pad preferably utilizes a known technique of "connection on the active area" and is located on one or more crystal blocks or crystal block portions. Using this combination technology, one or more wire bonds are attached to the source and body metallization layers, directly above the source and body and gate regions. The use of the active area on the connection increases the chip area with source and body areas, improves use, and eliminates the need for a dedicated "source connection pad" in the present invention. 6. The gate pad is preferably not connected to the source and body region of the crystal block, but is formed on any crystal block or group of crystal blocks. FIG. 10 depicts a detailed layout of the vertical DMOS device in FIG. 1. Although any size array can be used to make the vertical DMOS, the specific array 71 shown in FIG. 10 is a 7 × 9 array of crystal blocks 73. It should be noted that, of course, -11-(9) (9) 200403730 on each side belongs to the neighboring device, so the 7 x 9 array shown in Fig. 10 actually has an effective size of only 6 x 8 ingots. In the particular array shown, the gate pad 75 is located at the bottom center of the device, and the source pad 7 7 is located at the center of the device. The choice of an odd or even number of crystal blocks along each axis affects the position of the source and body pads, the position of the gate pads, and the symmetry of the device. The crystal block described in this article may allow multiple source pads and / or gate pads for each connection to be attached. This characteristic makes the manufacture of a considerable number of devices without significantly increasing the series impedance in the source and bulk metallization or in the gate conductor. So far, the ingots have been described to have the same length and width. However, it is also possible to use different lengths and widths in the device or in the method described herein. However, for optimal layout efficiency, if the length and width of the ingot are not equal, it is preferred that the longest dimension of the ingot is an integer multiple of the shortest dimension. The ingots shown in Figures 2 and 3 can be manufactured using trench technology and planar technology. If trench technology is used, only the polycrystalline silicon regions' forming the gate contacts 37a and 37b are located on the surface of the wafer. Figures 11 and 12 depict details of the ingot shown in Figures 2 and 3, which have a trench D M 0 S structure. A cross-sectional view of the grid viewed along line 1 1-1 1 in Figure 2 is depicted in Figure 1 1. This cross-sectional view is the same as the cross-sectional view viewed along axis 34 in FIG. 2 (that is, the crystal block is symmetrical) and the same as the cross-sectional view viewed along axis 36 in FIG. The cross-sectional view viewed along line 1 2-1 2 in Fig. 3 is depicted in Fig. 12 and is different from the cross-sectional view viewed along axis 36 (that is, the crystal block is asymmetric). The latter's cross-sectional view is the same as the cross-sectional view shown in Fig. 11. -12- (10) (10) 200403730 Referring to FIG. 11 and FIG. 12, the device depicted therein includes an N + substrate 91 and an epitaxial layer 93. A series of trenches 95 are formed in the epitaxial layer. Each trench is doped with polysilicon 97 and includes a gate oxide layer 99. Each trench is bounded by a double diffusion source and a body region 101, the latter including a source 103, a shallow diffusion P-type region 104, and a deep diffusion P + region 105. The source and body metallization layers 107 are present on the top surface and are connected to the source and body regions 101. As shown in Table 1, the grain size can be made into individual ingots with multiple columns and rows, and a single ingot can be used as the gate pad. From a manufacturing point of view, given the resulting aspect ratio, several grain sizes may not be very pleasing. For this example, a device with an aspect ratio greater than 3: 1 may not be easy to manufacture. In addition to the grain sizes listed in Table 1 and larger than those listed in Table 1, other grain sizes can be obtained. There is no specific upper limit on the size of individual arrays (each array has a single crystal block as a gate pad), but if the grain size grows too large, there may be manufacturing concerns. The minimum actual size of an individual array with a gate pad is determined by the number of active arrays relative to a single gate pad array. If the size of the individual array is smaller than 2 × 3 ingots, no active ingots are available for processing. At an individual array size of 2 x 3, the ratio of source and body bulk regions to gate pad bulk regions is 1: 1, which is too small to be practical for many applications. (11) 200403730 Table 1: Ingot design of devices of different sizes.Internal crystals of the internal array source and main gate crystals. Horizontal and vertical. The number of internal crystal blocks and the number of blocks. Total number of crystal blocks Proportion of total crystal blocks 2 1x2 1 1 2 3 2: 6 3 1x3 2 1 2 4 3: 8 4 2x2 3 1 3 3 4: 9 6 2x3 5 1 3 4 6:12 8 2x4 7 1 3 5 8:15 9 3x3 8 1 4 4 9:16 10 2x5 9 1 3 6 10:18 12 3x4 11 1 4 5 12:20 15 3x5 14 1 4 6 15:24 18 3x6 17 1 4 7 18:28 20 4x5 19 1 5 6 20:30 25 5x5 24 1 6 6 25:36 30 5x6 29 1 6 7 30:42 35 5x7 34 1 6 8 35:48 40 5x8 39 1 6 9 40:54 49 7x7 48 1 8 8 49:64 64 8x8 63 1 9 9 64:81 81 9x9 80 1 10 10 81: 100 100 10x 10 99 1 11 11 100: 121 (12) (12) 200403730 using a previously manufactured crystal block to produce For each new installation, contact masks, metal masks, and pad masks are required. By including dedicated gate pad masks at regular intervals in the sub-array, the need for individual contact masks for each new device can be eliminated. The position of the dedicated gate pad mask in the sub-array can be selected to provide one or more gate pads per die. In some embodiments, the dedicated gate pad crystal block has the same rocky layer geometry as the active crystal block and has a host dopant, but currently has no source dopant and is not in electrical contact with the body region. In other embodiments, the dedicated gate pad crystal block has a continuous polysilicon geometry, and only the outer edge matches the geometry of the active crystal block. The host dopant currently continues under the polysilicon and is electrically floating or in contact with the source and host terminals. Various other polysilicon geometries and dopant locations can be used to achieve electrical contact with the gate without affecting the electrical performance of the crystal block or without significantly increasing the impedance of the device line. An odd or even number of active crystal blocks are arranged between the gate pad crystal blocks in the horizontal and vertical directions. If an odd number is selected between the gate pad crystals on each axis, a larger symmetry will be obtained. The exact number of active crystal blocks between the gate pad crystal blocks in each direction determines the grain size of the same crystal grains allowed. In the device 1 1 1 in FIG. 13, for example, there are 5 active crystal blocks 1 1 5 a between the gate pad crystal blocks 1 1 3 a in the horizontal direction and 7 active crystal blocks in the vertical direction. In the whole sub-array 1 17a, the number of columns and rows is calculated, and there are 6 rows and 8 columns in total. Devices can be designed using any number of sub-arrays, each of which has a gate pad crystal block. In the example shown in Figures 1 to 15, three representative grain sizes can be obtained 'shown as a 5 X 7 sub-array, along with three possible sub-array arrangements of -15- (13) 200403730 1 1 7 a , 1 1 7 b and 1 1 7 c. Thus, FIG. 13 depicts a device including a 3 × 3 arrangement of sub-arrays 11 7a. Figure 14 depicts a 1 × 2 array of orientations 1 1 9, and FIG. 15 depicts an 2 × 3 array of orientations 1 2 1. Table 2 lists several other possible devices consisting of the sub-array shown in Figure 15. -16- (14) 200403730 Table 2: Arrangement of sub-arrays with dedicated gate pads and containing 6x8 crystal blocks. Number of sub-arrays. Orientation of sub-arrays. Number of blocks than appearance ratio 1 1x1 6 8 34:48 3: 4 2 1x2 6 16 73:96 3: 8 2 2x1 12 8 75:96 3: 2 3 1x3 6 24 112: 144 1: 4 3 3x1 18 8 116 : 144 9: 4 4 1x4 6 32 151: 192 3:16 4 2x2 12 16 161: 192 3: 4 4 4x1 24 8 157: 192 3: 1 5 1x5 6 40 190: 240 3:20 5 5x1 30 8 198 : 240 15: 4 6 1x6 6 48 229: 288 1: 6 6 2x3 12 24 247: 288 1: 2 6 3x2 18 16 249: 288 9: 8 6 6x1 36 8 239: 288 9: 2 7 1x7 6 56 268 : 336 3:28 7 7x1 42 8 280: 336 21: 4 8 1x8 6 64 307: 384 3:32 8 2x4 12 32 333: 384 3: 8 8 4x2 24 16 337: 384 3: 2 8 8x1 48 8 321 : 384 6: 1 9 1x9 6 72 346: 432 1:12 9 3x3 18 24 382: 432 3: 4 9 9x1 54 8 362: 432 27: 4

-17- (15) (15)200403730 若將獲得所需崩潰電壓，則利用可於製造程序後期組 建之晶塊陣列，以產生不同尺寸的MOS閘裝置，並在晶 塊設計上設定若干特定要求。該些要求產生下列晶塊佈局 的指導方針： 1 ·每一晶塊的源極及主體區應與所有其他晶塊的源極 及主體區隔離。 2.每一晶塊的閘極應與所有其他晶塊的閘極隔離。 3 ·當晶塊與終端均適當金屬化時，單一金屬化晶塊應 可支撐所需崩潰電壓。 4·當晶塊與終端均適當金屬化時，任一數量晶塊應可 支撐所需崩潰電壓。 5 ·當與形成標線及邊緣終端外緣之晶塊的閘極區電氣 接觸時，源極擴散與主體擴散的合成應可支撐所需崩潰電 壓。 渠等指導方針可應用於每一獨特晶塊設計，以獲得所 需崩潰電壓。下列將說明應用特定技術所製造的裝置。 使用例如圖2-3所顯示之閘極結構所製造的平面M0S 閘裝置，需要終端結構。如上述，每一晶塊幾何圖形必須 依循五項指導方針，同時將裝置線上阻抗減至最低。裝置 線上阻抗的最小化，可透由使用具最低阻値之半導體材 料，獲得最大崩潰電壓而達成。晶塊終端結構與製造程序 的最佳化是必須的。 圖1 6 -1 9所示終端結構1 3 1 a - d，可用於低電壓、平面 Μ Ο S閘裝置。每一結構包括多砂閘極1 3 3，其被壓縮於電 -18- (16) (16)200403730 介値135中，並暴露於源極區137與主體區139之上。在 所示特定裝置中’主體區包括淺擴散區1 4 1與深擴散區 1 4 3。金屬化層1 4 5延伸跨越提供與擴散區連接之裝置的 表面。若邊緣接合爲非主動，則鄰近邊緣之閘極區可電氣 浮動，但若邊緣接合爲主動，則需與閘極持續電氣接觸。 圖1 6- 1 9所示範例並非窮舉表列，但代表可使用之典 型的終端技術。具主動接合之終端結構的使用，增加了流 經裝置的電流，但在晶塊區僅略微增加。該主動終端結構 除支撐崩潰電壓外，並有助於電流流經裝置，而被動終端 結構則僅支撐崩潰電壓。 圖1 1-12所示之溝MOS閘裝置，亦具有多樣不同的 晶塊佈局與製造程序，其產生所需崩潰電壓。產生終端結 構151a-d的範例顯示於圖20-23中。如其中所示，每一 結構包括一系列的溝1 5 3，其於裝置之外延層1 5 5中形 成。每一溝塡注摻雜多矽物1 5 7，並包括閘極氧化物層 1 5 9。每溝以雙擴散源極及本體區1 6 1爲界，後者可包括 例如淺擴散P型區163及深擴散P+區165。N+摻雜源極 區1 6 7配置於溝的頂端，亦與金屬化層1 6 9電氣接觸。該 些各式終端結構及其他終端結構，可用於每一晶塊，以獲 致最佳線上阻抗。如同平面終端結構，若邊緣接合爲非主 動，則鄰近邊緣之閘極區可電氣浮動，但若邊緣接合爲主 動，則需與閘極持續電氣接觸。 雖然本文已具體描述與說明各式實施例，但應理解的 是，在上述理論涵蓋且不偏離申請專利之精神與範圍下， -19- (17) (17)200403730 本發明可進行修改與變化。此外，該些範例不應解譯爲侷 限申請專利所涵蓋之本發明的修改與變化’而僅爲可能變 化的描述。 【圖式簡單說明】 圖1爲使用相同晶塊的7 X 9陣列，所形成之MO S閘垂 直DMOS裝置的槪要圖。 圖2描繪具源極及本體佈局之晶塊’該佈局在X軸與γ 軸相同。該佈局可用於平面及溝形MOSFET (金屬氧化物 半導體場效電晶體）。溝形MOSFET在溝中具有闊極多石夕 物，而在晶圓表面上的每一角落僅具有多矽物區。 圖3描繪具源極及本體佈局之晶塊，該佈局在X軸與γ 軸不同。該佈局可用於平面及溝形MOSFET。溝形 MOSFET在溝中具有閘極多砂物，而在晶圓表面上的每一 角落僅具有多矽物區。 圖4至6描繪晶塊陣列或晶片中的內側金屬化層。 圖7至9描繪晶塊陣列或晶片角落外側金屬化層。 圖10細部描繪M0S閘垂直DM0S或溝形DMOS裝置的 佈局。 圖1 1爲圖2之線Π -1 1沿線截面圖。 圖12爲圖3之線12-12沿線截面圖。 圖1 3描繪6晶塊乘以8晶塊之次陣列的3 X 3排列，每一 次陣列均配置一墊晶塊。 圖1 4描繪晶塊的1 X 2陣列，其在標線附近配置一閘極 -20- (18) 200403730 墊晶塊。 圖1 5描繪晶塊的3 X 2陣列，其具有用於閘極接點的閘 極墊晶塊。 圖1 6描繪在具均勻厚度且無邊緣摻雜之閘極下方，具 氧化物的聞極場。 圖1 7描繪在無邊緣摻雜之閘極的外緣下方，具較厚氧 化物的閘極場。 圖1 8描繪具閘極外側非主動接合之擴散接合終端。 圖1 9描繪部分或整個邊緣具非主動接合之擴散接合終 端。 圖2 0描繪具邊緣溝做爲終端之溝形終端結構。 圖2 1描繪具邊緣溝之多矽物做爲場板的溝形終端結 構。 圖22描繪具支撐反向電壓之邊緣溝外側被動接合的溝 形終端結構。 圖2 3描繪具支撐反向電壓之邊緣溝外側主動接合的溝 形終端結構。 【符號說明】 11、 43a-c 、 61 、 61b-c 13、 15、 21、 21a-b、 41a-d 17 31a-b、 101 、 161 33a-b 、 35a-b 、 74-17- (15) (15) 200403730 If the required breakdown voltage is to be obtained, use an array of crystal blocks that can be constructed later in the manufacturing process to generate MOS gate devices of different sizes, and set certain specific requirements on the design of the crystal block . These requirements result in the following guidelines for the layout of the ingots: 1 The source and body regions of each ingot should be isolated from the sources and body regions of all other ingots. 2. The gate of each crystal block should be isolated from the gate of all other crystal blocks. 3 • When the ingot and terminal are properly metallized, a single metallized ingot should be able to support the required breakdown voltage. 4. When the ingot and terminal are properly metallized, any number of ingots should be able to support the required breakdown voltage. 5 · When in electrical contact with the gate area of the crystal block forming the reticle and the outer edge of the edge termination, the combination of source diffusion and body diffusion should support the required breakdown voltage. Guidelines such as canals can be applied to each unique die design to achieve the required breakdown voltage. The following will describe devices made using specific techniques. A planar MOS gate device manufactured using, for example, the gate structure shown in Figure 2-3 requires a termination structure. As mentioned above, each block geometry must follow five guidelines while minimizing line impedance on the device. Minimizing the line impedance of the device can be achieved by using a semiconductor material with the lowest resistance to obtain the maximum breakdown voltage. Optimization of the wafer termination structure and manufacturing process is required. The terminal structures 1 3 1 a-d shown in Figs. 16 to 19 can be used for low-voltage, planar MOS gate devices. Each structure includes a multiple-sand gate 133, which is compressed in the dielectric 135- (16) (16) 200403730 and exposed to the source region 137 and the body region 139. In the particular device shown, the ' body region includes a shallow diffusion region 141 and a deep diffusion region 143. The metallization layer 1 4 5 extends across the surface of the device providing a connection to the diffusion region. If the edge joint is inactive, the gate area adjacent to the edge can be electrically floating, but if the edge joint is active, continuous electrical contact with the gate is required. The examples shown in Figures 16-19 are not exhaustive, but represent typical terminal technologies that can be used. The use of a terminal structure with active bonding increases the current through the device, but only slightly increases in the crystal block area. In addition to supporting the breakdown voltage, the active termination structure helps current flow through the device, while the passive termination structure only supports the breakdown voltage. The trench MOS gate device shown in Fig. 1 1-12 also has a variety of different crystal block layouts and manufacturing procedures, which generate the required breakdown voltage. Examples of generating terminal structures 151a-d are shown in Figures 20-23. As shown therein, each structure includes a series of trenches 153 formed in the epitaxial layer 155 of the device. Each trench is doped with polysilicon 1 5 7 and includes a gate oxide layer 1 5 9. Each trench is bounded by a dual diffusion source and a body region 161, which may include, for example, a shallow diffusion P-type region 163 and a deep diffusion P + region 165. The N + doped source region 16 is disposed at the top of the trench and is also in electrical contact with the metallization layer 169. These various termination structures and other termination structures can be used for each crystal block to obtain the best line impedance. Like the planar termination structure, if the edge joint is non-active, the gate area adjacent to the edge can be electrically floating, but if the edge joint is active, continuous electrical contact with the gate is required. Although various embodiments have been specifically described and illustrated herein, it should be understood that, within the scope of the above theory and without departing from the spirit and scope of the patent application, -19- (17) (17) 200403730 may be modified and changed. . In addition, these examples should not be interpreted as a description of the modifications and changes of the invention covered by the patent application, but only as possible changes. [Brief description of the figure] Fig. 1 is a schematic diagram of a MOS gate vertical DMOS device formed by a 7 X 9 array using the same crystal block. Fig. 2 depicts a crystal block ' with a source and body layout which is the same on the X-axis and the γ-axis. This layout can be used for planar and trench MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Trench MOSFETs have extremely large amounts of silicon in the trenches, while each corner on the surface of the wafer has only polysilicon regions. FIG. 3 depicts a crystal block with a source and body layout, which is different in the X-axis and the γ-axis. This layout can be used for both planar and trench MOSFETs. Trench MOSFETs have gate-rich sand in the trench, while each corner on the wafer surface has only silicon-rich regions. 4 to 6 depict an inner metallization layer in an array of wafers or a wafer. Figures 7 to 9 depict metallization layers on the outside of a chip array or wafer corner. Figure 10 details the layout of the MOS gate vertical DMOS or trench DMOS device. FIG. 11 is a cross-sectional view taken along the line II-1-11 of FIG. 2. FIG. 12 is a sectional view taken along line 12-12 of FIG. 3. FIG. Figure 13 depicts a 3 X 3 arrangement of a 6-by-8 multi-by-sub array, with each sub-array configured with a pad. Figure 14 depicts a 1 X 2 array of crystal blocks with a gate -20- (18) 200403730 pad crystal block placed near the marked line. Figure 15 depicts a 3 X 2 array of crystal blocks with gate pad crystal blocks for gate contacts. Figure 16 depicts an oxide field under the gate with a uniform thickness and no edge doping. Figure 17 depicts a gate field with thicker oxides below the outer edge of the gate without edge doping. Figure 18 depicts a diffusion-junction terminal with inactive junctions outside the gate. Figure 19 depicts a diffusely bonded termination with inactive joints in part or all of its edges. Figure 20 depicts a grooved terminal structure with a marginal groove as a terminal. Figure 21 depicts a trench-shaped termination structure with multiple silicon objects as edge plates as field plates. Figure 22 depicts a grooved terminal structure with passive joints on the outside of the edge groove supporting the reverse voltage. Figure 23 depicts a grooved terminal structure with an active joint outside the edge groove supporting the reverse voltage. [Explanation of symbols] 11, 43a-c, 61, 61b-c 13, 15, 21, 21a-b, 41a-d 17 31a-b, 101, 161 33a-b, 35a-b, 74

陣歹IJ 6 5 - 6 8、7 3、1 1 3、1 1 5 a 晶塊 標線 源極及本體區 元件 -21 - (19) 200403730 34、36 37a-b、 45、 69a、 72 46 47a-c、 63a 5 1、69c、7 1 a-b、1 07 5 3 7 0 a - c 75 77 9 1 93 97 、 157 99 、 159 103、 137、 167 104、 163 105、 165 111 117a-c 119、 121 131a-d、 151a-d 1 33 13 5 1 39 14 1 軸 閘極接點墊 間隙 閘極金屬化層 源極及本體金屬化層 空間或溝 終端金屬化層 閘極墊 源極墊 基底 外延層 多矽物 閘極氧化物層 源極 淺擴散P型區 深擴散P +區 裝置 次陣歹IJ 方位 終端結構 多砂物閘極 電介質 本體 淺擴散區 - 22- (20)200403730 143 145 1 53 15 5 169 深擴散區 金屬化層 溝 外延層 -23-Array IJ 6 5-6 8, 7 3, 1 1 3, 1 1 5 a Crystal line source and body area components -21-(19) 200403730 34, 36 37a-b, 45, 69a, 72 46 47a-c, 63a 5 1, 69c, 7 1 ab, 1 07 5 3 7 0 a-c 75 77 9 1 93 97, 157 99, 159 103, 137, 167 104, 163 105, 165 111 117a-c 119 , 121 131a-d, 151a-d 1 33 13 5 1 39 14 1 shaft gate contact pad gap gate metallization source and body metallization space or trench terminal metallization gate pad source pad substrate Epitaxial layer polysilicon gate oxide layer source shallow diffusion P-type region deep diffusion P + region device sub-array 歹 IJ azimuth termination structure multi-sand gate dielectric dielectric body shallow diffusion region 53 15 5 169 Metallized layer trench epitaxial layer in deep diffusion region -23-

Claims (1)

(1) (1)200403730 拾、申請專利範圍 1 ·一種製造MOS閘裝置的方法，包括以下步驟： 提供複數個獨立的晶塊，各具有至少一源極區，及至 少一本體區；及 將該些晶塊納入一陣列，以形成一 Μ 0 S閘裝置。 2 ·如申請專利範圍第1項之方法，其中該複數個晶塊 基本上相同。 3 ·如申請專利範圍第1項之方法，其中每一該複數個 晶塊基本上爲矩形。 4 ·如申g靑專利範圍第1項之方法，其中每一該複數個 晶塊基本上爲方形。 5 .如申請專利範圍第1項之方法，其中每一晶塊具有 複數個鬧極接點區分佈其上。 6 ·如申請專利範圍第5項之方法，其中每一晶塊基本 上爲矩形，而且其中每一晶塊的每一角落具有閘極接點區 分佈其上。 7 ·如申請專利範圍第5項之方法，其中每一晶塊基本 上爲方形’而且其中每一晶塊的每一角落具有閘極接點區 分佈其上。 8 ·如申請專利範圍第1項之方法，其中每一晶塊包含 複數個源極及本體區，而且其中複數個源極及本體區配置 於次陣列中。 9.如申請專利範圍第1項之方法，其中該陣列進一步 包括一閘極金屬化層。 -24- (2) (2)200403730 I 0 .如申請專利範圍第1項之方法，其中該陣列進一步 包括一源極及本體金屬化層。 II ·如申請專利範圍第1項之方法，其中該陣列進一步 包括一閘極金屬化層，及一源極及本體金屬化層，而其中 該閘極金屬化層與該源極及本體金屬化層，彼此電氣絕 緣。 1 2 ·如申請專利範圍第1項之方法，其中至少若干該複 數個晶塊包括一外延層，其具有至少一溝分佈其中，而其 中該至少一溝具有部分摻雜多矽物分佈其中。 1 3 ·如申g靑專利範圍第1項之方法’其中至少一個該複 數個晶塊包括一閘極結構。 Ϊ 4 ·如申請專利範圍第丨3項之方法，其中該閘極結構 的部分爲電氣浮動。 15· —種MOS閘裝置，包含： 個別晶塊的陣列，其中該陣列的每一晶塊具有源極 區、本體區及閘極接點區； 源極及本體金屬化層與該陣列中至少二晶塊的源極及 本體區電氣接觸；及 閘極金屬化層則與該陣列中至少二晶塊的閘極接點電 氣接觸。 1 6.如申請專利範圍第〗5項之裝置，其中該陣列中每 一晶塊具有四個閘極接點區，而對任一未鄰近陣列邊緣的 晶塊而言’其中閘極金屬化層與至少兩個閘極接點電氣接 觸。 (3) (3)200403730 1 7 ·如申請專利範圍第1 6項之裝置，其中該閘極金屬 化層與陣列中至少若千晶塊的恰好兩個閘極接點區電氣接 觸。 1 8 .如申請專利範圍第1.5項之裝置，其中每一該複數 個晶塊在陣列中藉間隙而彼此分離，其中源極及本體金屬 化層延伸跨越間隙。 1 9 ·如申請專利範圍第1 5項之裝置，其中該閘極金屬 化層包括複數個分離的金屬帶。 2 0 ·如申請專利範圍第1 9項之裝置，其中每一該複數 個分離的金屬帶受該源極及本體金屬化層環繞，但空間分 離。 2 1 ·如申請專利範圍第1 5項之裝置，進一步包括一源 極墊。 2 2 ·如申g靑專利範圍第1 5項之裝置，進一步包括一閘 極墊。 2 3 ·如申請專利範圍第1 5項之裝置，其中該複數個晶 塊基本上相同。 24·如申請專利範圍第15項之裝置，其中每一該複數 個晶塊基本上爲矩形。 25.如申請專利範圍第15項之裝置，其中每一該複數 個晶塊基本上爲方形。 26·如申請專利範圍第15項之裝置，其中每一晶塊基 本上爲矩形’而且其中每一晶塊的每一角落具有閘極接點 區分佈其上。 -26- (4) (4)200403730 27·如申請專利範圍第15項之裝置，其中每一晶塊基 本上爲方形，而且其中每一晶塊的每一角落具有閘極接點 區分佈其上。 2 8 ·如申請專利範圍第1 5項之裝置，其中該陣列進__ 步包括一閘極金屬化層，及一源極及本體金屬化層，而其 中該閘極金屬化層與該源極及本體金屬化層，彼此電氣絕 緣。 2 9 ·如申請專利範圍第1 5項之裝置，其中至少若干該 陣列中之晶塊包括一外延層，其具有至少一溝分佈其中， 而其中該溝具有部分摻雜多矽物分佈其中。 3 〇 ·如申請專利範圍第1 5項之裝置，其中至少一個該 陣列之晶塊包括一閘極結構。 3 1 ·如申請專利範圍第1 5項之裝置，其中該閘極結構 的部分爲電氣浮動。 32·—種MOS閘裝置，包含： 個別晶塊的陣列，該陣列包括沿陣列外側分佈的第一 複數個晶塊，及分佈於陣列內側的第二複數個晶塊，其中 每一該第一及第二複數個晶塊，具有源極及本體區，與閘 極接點區； 一源極及本體金屬化層，其與第二複數個晶塊的源極 及本體區電氣接觸；及 一終端金屬化層，其與每一該第一複數個晶塊中至少 一源極及本體區’及至少一閘極接點區電氣接觸。 3 3 ·如申請專利範圍第3 2項之裝置，其中該終端金屬 -27- (5) (5)200403730 化層與每一該第一複數個晶塊中的每一源極區、每一本體 區及至少一閘極接點電氣接觸。 3 4 .如申請專利範圍第3 2項之裝置，進一步包括一閘 極金屬化層，其與至少二個該第二複數個晶塊之閘極接點 區電氣接觸。 3 5 .如申請專利範圍第3 2項之裝置，其中該陣列包括 至少四個晶塊。 3 6 .如申請專利範圍第3 2項之裝置，其中該陣列包括 至少六個晶塊。 3 7 .如申請專利範圍第3 2項之裝置，其中該陣列包括 至少八個晶塊。 3 8 .如申請專利範圍第3 2項之裝置，進一步包括一閘 極墊。 3 9.如申請專利範圍第32項之裝置，進一步包括一源 極及本體墊。(1) (1) 200403730 Patent application scope 1 · A method for manufacturing a MOS gate device, comprising the steps of: providing a plurality of independent crystal blocks, each having at least one source region, and at least one body region; and The crystal blocks are incorporated into an array to form an M 0 S gate device. 2. The method of claim 1 in which the plurality of crystal blocks are substantially the same. 3. The method of claim 1 in the scope of patent application, wherein each of the plurality of crystal blocks is substantially rectangular. 4. The method of claim 1 of the patent scope, wherein each of the plurality of crystal blocks is substantially square. 5. The method of claim 1 in the scope of patent application, wherein each crystal block has a plurality of anode contact areas distributed thereon. 6. The method according to item 5 of the scope of patent application, wherein each crystal block is substantially rectangular, and each corner of each crystal block has a gate contact region distributed thereon. 7. The method according to item 5 of the scope of patent application, wherein each crystal block is substantially square 'and wherein each corner of each crystal block has a gate contact region distributed thereon. 8. The method according to item 1 of the scope of patent application, wherein each crystal block includes a plurality of source and body regions, and wherein the plurality of source and body regions are arranged in a sub-array. 9. The method of claim 1, wherein the array further includes a gate metallization layer. -24- (2) (2) 200403730 I 0. The method according to item 1 of the patent application range, wherein the array further includes a source electrode and a bulk metallization layer. II. The method of claim 1, wherein the array further includes a gate metallization layer, and a source and body metallization layer, and wherein the gate metallization layer and the source and body metallization Layers, electrically insulated from each other. 1 2. The method of claim 1, wherein at least some of the plurality of crystal blocks include an epitaxial layer having at least one trench distributed therein, and wherein the at least one trench has a partially doped polysilicon distributed therein. 1 3. The method of claim 1 of the patent scope, wherein at least one of the plurality of crystal blocks includes a gate structure. Ϊ 4 · The method according to item 丨 3 of the patent application scope, wherein the part of the gate structure is electrically floating. 15. · A MOS gate device comprising: an array of individual crystal blocks, wherein each crystal block of the array has a source region, a body region, and a gate contact region; the source and the body metallization layer are at least in the array. The source and body regions of the two crystal blocks are in electrical contact; and the gate metallization layer is in electrical contact with the gate contacts of at least two crystal blocks in the array. 16. The device according to item 5 of the patent application, wherein each crystal block in the array has four gate contact areas, and for any crystal block that is not adjacent to the edge of the array, where the gate is metallized The layer is in electrical contact with at least two gate contacts. (3) (3) 200403730 1 7 • For the device under the scope of application for patent No. 16, wherein the gate metallization layer is in electrical contact with at least two gate contact areas of at least two thousand crystal blocks in the array. 18. The device according to item 1.5 of the scope of patent application, wherein each of the plurality of crystal blocks are separated from each other by a gap in the array, wherein the source electrode and the bulk metallization layer extend across the gap. 19. The device according to item 15 of the patent application, wherein the gate metallization layer comprises a plurality of separated metal strips. 20 · The device according to item 19 of the scope of patent application, wherein each of the plurality of separated metal strips is surrounded by the source electrode and the bulk metallization layer, but space is separated. 2 1 · The device according to item 15 of the patent application scope further includes a source pad. 2 2 · The device according to item 15 of the patent application scope further includes a gate pad. 2 3 · The device according to item 15 of the scope of patent application, wherein the plurality of crystal blocks are substantially the same. 24. The device as claimed in claim 15 wherein each of said plurality of crystal blocks is substantially rectangular. 25. The device as claimed in claim 15 wherein each of said plurality of crystal blocks is substantially square. 26. The device according to item 15 of the scope of patent application, wherein each crystal block is substantially rectangular 'and each corner of each crystal block has a gate contact region distributed thereon. -26- (4) (4) 200403730 27. For the device under the scope of application for patent No. 15, wherein each crystal block is substantially square, and each corner of each crystal block has a gate contact area to distribute it. on. 2 8 · The device according to item 15 of the patent application range, wherein the array further includes a gate metallization layer, a source electrode and a bulk metallization layer, and wherein the gate metallization layer and the source The electrode and the body metallization layer are electrically insulated from each other. 29. The device according to item 15 of the patent application, wherein at least some of the crystal blocks in the array include an epitaxial layer having at least one trench distributed therein, and wherein the trench is partially doped with polysilicon distributed therein. 30. The device according to item 15 of the patent application, wherein at least one of the crystal blocks of the array includes a gate structure. 3 1 · The device according to item 15 of the scope of patent application, wherein the part of the gate structure is electrically floating. 32 · —A MOS gate device, comprising: an array of individual crystal blocks, the array including a first plurality of crystal blocks distributed along an outer side of the array, and a second plurality of crystal blocks distributed inside an array, each of the first And a second plurality of crystal blocks, having a source and a body region, and a gate contact region; a source and a body metallization layer, which are in electrical contact with the source and body regions of the second plurality of crystal blocks; and The terminal metallization layer is in electrical contact with at least one source and body region 'and at least one gate contact region in each of the first plurality of crystal blocks. 3 3 · The device according to item 32 of the scope of patent application, wherein the terminal metal -27- (5) (5) 200403730 formation layer and each source region, each of the first plurality of crystal blocks The body area and at least one gate contact are in electrical contact. 34. The device according to item 32 of the scope of patent application, further comprising a gate metallization layer, which is in electrical contact with the gate contact areas of at least two of the second plurality of crystal blocks. 35. The device of claim 32, wherein the array includes at least four crystal blocks. 36. The device of claim 32, wherein the array includes at least six crystal blocks. 37. The device of claim 32, wherein the array includes at least eight crystal blocks. 38. The device according to item 32 of the scope of patent application, further comprising a gate pad. 3 9. The device according to item 32 of the scope of patent application, further comprising a source electrode and a body pad.
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