CN100530568C - Surface geometry for a MOS-gated device - Google Patents

Surface geometry for a MOS-gated device Download PDF

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Publication number
CN100530568C
CN100530568C CNB038106094A CN03810609A CN100530568C CN 100530568 C CN100530568 C CN 100530568C CN B038106094 A CNB038106094 A CN B038106094A CN 03810609 A CN03810609 A CN 03810609A CN 100530568 C CN100530568 C CN 100530568C
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paster
source
grid
metal layer
array
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CN1653602A (en
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理查德·A·布朗夏尔
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General Semiconductor Inc
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General Semiconductor Inc
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Priority claimed from US10/142,600 external-priority patent/US6710414B2/en
Priority claimed from US10/142,622 external-priority patent/US6861337B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A surface geometry for a MOS-gated device is provided that allows device size to be varied in both the x-axis and the y-axis by predetermined increments. The actual device size is set or ''programmed'' by the metal and pad masks or the contact metal and pad masks. This approach saves both time and expense. A 7X9 array (11) of identical tiles (13) is shown.

Description

The mos gate device making method
Technical field
The present invention relates generally to mos gate device and manufacture method thereof.
Background technology
The surface geometry that is used to make the mos gate device is developed widely.These surface geometries or " layout " comprise interdigitated structure and repetition or " honeycomb " structure, comprise with
Figure C0381060900041
Power MOSFET is the known hexagon geometry of example.These various surface geometries are developed, to optimize such as device properties such as conducting resistance and intensity.For given geometry and voltage, the conducting resistance of device and active parts area are inversely proportional to.The new unit that has required conducting resistance in order to adopt existing surface geometry to design only need calculate the conducting resistance of existing device and the product of its effective area.Based on this information, determine the effective area of new unit, add the expense of pad and terminal, just can produce device with required conducting resistance.
But, for each different conduction resistance value or mos gate device size that each is different are all made the new mask of a cover, this traditional method is very unfavorable, because this can cause producing a large amount of mask set, is used for those mainly different devices aspect conducting resistance and effective area.And each device all must carry out verification of conformity respectively before dispatching from the factory.Traditional devices does not provide a kind of simple and easy method yet, promptly adopts removable grid of this method and source pad to adapt to special final use.
Therefore, this area needs a kind of method of making the mos gate device, only needs mask set just can produce device, and can adopt same set of mask to produce variable-sized and the mos gate device with different conducting resistance.This area also needs a kind of method of making the mos gate device, and this type of device of gang is all provable like this is qualified, and needn't prove that each certain device is qualified in this family.At last, this area needs a kind of surface design that is used for the mos gate device, and its allows so that adapt to specific final use, and not need a large amount of design iterations work at device inside be easy to move around grid and source pad.These need and can be met by method disclosed herein and device.
Summary of the invention
Die face (modular surface) geometry that is used for the mos gate device and the method for making the mos gate device with these surface geometries are disclosed at this.By predetermined increment, these die face geometries allow device size to change along x axle and y axle.
Among some embodiment of Apparatus and method for disclosed herein, the practical devices size is through setting or by contact, metal and pad mask " programming ", and in other embodiments, device size is only programmed by metal and pad mask.This method is not only saved time but also reduce expenses, because only need new contact, metal and pad mask for each new unit, or new metal and pad mask.In addition, the wafer (wafer) that can prefabricatedly be used for these devices was stored in the stock place with it before contact or metal mask, therefore, just allowed to carry out most of manufacture process before learning the detail of device.Conversely, this has greatly reduced the manufacturing required time of new unit.
One family device that can prove manufacturing in this way is qualified, and needn't prove that each certain device is qualified.In addition, the position of moving source and grid bonding welding pad is used for being integrated into new encapsulation or is used for new application easily.Therefore, this method provides a kind of possibility easily, generates the new mask that a whole set of is used for each required new unit.
In one aspect, openly be used to make the method for mos gate device at this.According to this method, a plurality of discontinuous pasters (tile) are provided, wherein each paster all comprises at least one source region and at least one tagma.Each paster typical case comprises a plurality of arrangements gate contact zone thereon.A plurality of pasters are combined into array, so that form the mos gate device.Preferably, the size of paster is identical basically.Equally, the shape of paster is preferably rectangle or square.The grid metal layer, it can be for example a series of discontinuous metal trace (trace), be positioned to the described array of small part, so that the gate contact zone in it and the array electrically contacts.Source and body metal layer are positioned to the described array of small part, so that the source and the tagma of it and paster electrically contact.The terminal metal layer also can be positioned on the paster that forms the device outer periphery, and the typical case is positioned on these pasters, so that the gate contact zone of it and outer periphery paster and source and body contact zone all electrically contact.
In one aspect of the method, mos gate device disclosed herein comprises a discontinuous patch array, and wherein, each paster in the described array all comprises source region, tagma and gate contact zone.Source and body metal layer are provided, and the source and the tagma of at least two pasters in it and the described array electrically contact, and the grid metal layer is provided, and the gate contact of at least two pasters in it and the described array electrically contacts.Preferably, each paster in the array comprises four gate contact zones, and for the paster that is positioned at array inside, wherein at least two gate contact zones contact with the grid metal layer.Paster typical arrangement in array becomes to make and has the gap between adjacent patch, and source and body metal layer preferably extend through this gap.Typically, grid metal layer and source and body metal layer are by keeping physical clearance or being electrically insulated from each other at interval between them.Paster in the array can comprise raceway groove or planar structure.
In aspect another, mos gate device provided herein comprises a discontinuous patch array.Described array comprises: more than first paster, arrange along array is outside; More than second paster is arranged in array inside.Each paster in more than first and second paster all comprises source and tagma and gate contact zone.Device also comprises: source and body metal layer, it and first and the source region and the tagma of more than two paster electrically contact; And the terminal metal layer, at least one source on each paster of it and described more than first paster and tagma and at least one gate contact zone electrically contact.
According to a first aspect of the invention, provide a kind of method of making the mos gate device, may further comprise the steps: a plurality of discontinuous pasters are provided, and each paster in described a plurality of discontinuous pasters has at least one source region and at least one tagma; And paster is assembled into array, so that form the mos gate device, wherein, along line by each outer periphery paster center, cutting forms the paster of device outer periphery, makes that the size of each outer periphery paster is half of size that is not positioned at the paster of device outer periphery.
According to a second aspect of the invention, provide a kind of mos gate device, having comprised: discontinuous array of patches, wherein, each paster in the described array comprises source region, tagma and gate contact zone; The source and the tagma of at least two pasters in source and the body metal layer, it and described array electrically contact; And the grid metal layer, the gate contact zone of at least two pasters in it and the described array electrically contacts.
According to a third aspect of the invention we, a kind of mos gate device is provided, comprise: discontinuous array of patches, described array comprises: more than first paster, arrange outside along array, and more than second paster, is arranged in array inside, wherein, each paster of described more than first and second pasters has source region, tagma and gate contact zone; Source and body metal layer, the source and the tagma of it and more than second paster electrically contact; And the terminal metal layer, at least one source region, at least one tagma and at least one gate contact zone on each paster of it and described more than first paster electrically contact.
Next these and other aspect to method disclosed herein and device describes in further detail.
Description of drawings
Fig. 1 shows the schematic diagram with the mos gate vertical DMOS device of the identical paster formation of 7 * 9 arrays.
Fig. 2 shows along the schematic diagram of the paster of x axle source identical with the y direction of principal axis and body layout.This layout both can be used for planar MOSFET and also can be used for channel mosfet.Channel mosfet comprises gate polysilicon in raceway groove, multi-crystal silicon area is only in the corner of each on crystal column surface.
Fig. 3 shows along the schematic diagram of the paster of x axle source different with the y direction of principal axis and body layout.This layout both can be used for planar MOSFET and also can be used for channel mosfet.Channel mosfet comprises gate polysilicon in raceway groove, multi-crystal silicon area is only in the corner of each on crystal column surface.
Fig. 4-6 shows the schematic diagram of the internal metallization layer of patch array or chip.
Fig. 7-9 shows the schematic diagram of patch array or chip exterior corner metal layer.
Figure 10 shows the detailed maps of mos gate vertical DMOS or raceway groove DMOS device layout.
Figure 11 is the profile along the line 11-11 intercepting of Fig. 2.
Figure 12 is the profile along the line 12-12 intercepting of Fig. 3.
Figure 13 shows the schematic diagram that 3 * 3 in 6 * 8 paster subarrays are arranged, and wherein each paster all is furnished with a pad paster.
Figure 14 shows near be furnished with 1 * 2 array plaster of grid pad paster the line schematic diagram.
Figure 15 shows the schematic diagram of 3 * 2 array plasters that comprise the grid pad paster that is used for gate contact.
Figure 16 shows has below the grid oxidated layer thickness evenly and do not have a schematic diagram of the grid field that periphery mixes.
Figure 17 shows thicker and do not have a schematic diagram of the grid field that periphery mixes in the outer peripheral oxide layer of grid.
Figure 18 shows the schematic diagram of the diffusion terminal of the outside no active junction of gate polysilicon (poly).
Figure 19 shows the schematic diagram that some or all peripheries all comprise the diffused junction terminal of a passive knot.
Figure 20 shows the schematic diagram of circumferential channel as the raceway groove terminal structure of terminal.
Figure 21 shows the schematic diagram of the polysilicon of circumferential channel as the raceway groove terminal structure of field plate (field plate).
The passive knot that Figure 22 shows the circumferential channel outside is kept the schematic diagram of the raceway groove terminal structure of reverse voltage.
The active junction that Figure 23 shows the circumferential channel outside is kept the schematic diagram of the raceway groove terminal structure of reverse voltage.
Embodiment
The mould layout geometry that is used for the mos gate device disclosed herein, it allows to adopt predetermined incremental mode that size of devices is changed along x axle and y axle, and disclosed herein these layout geometries only are used to make with mask set with regard to the method for the mos gate device of variable-size and conducting resistance (promptly, these methods only are required to be the new contact of each new unit manufacturing, metal and pad mask, or new metal and pad mask).According to method disclosed herein, can walk abreast and use a plurality of essentially identical pasters, to obtain device array with required size and conducting resistance.
In the discussion below with reference to accompanying drawing, same reference number is interpreted as the same element of expression.
The basis designed device total arrangement of disclosed principle has herein been described among Fig. 1.Show 7 * 9 arrays 11 of identical paster 13.Practical devices is made of 6 * 8 array plasters, because in the finished product device, outer periphery paster 15 has been cut (seeing the element 74 of Figure 10, the line chart example in another 7 * 9 array) along line 17.Therefore, the actual paster that comprises half of each outer periphery paster in the device of finishing.Select the size of basic paster,, and extend through line, to be formed on four adjacent wafer (die) (not shown) of level and vertical direction and at the edge termination of adjacent other four wafers of corner so that the outer periphery of paster forms the terminal of device.Each paster is preferably square or rectangle, and any two pasters preferably have same size.In addition preferably, the length of each paster and wide identical (being that paster is preferably square).
Fig. 2-3 shows two typical patch type, is used in the practice of method disclosed herein.Among the paster 21a shown in Figure 2, when along line 11-11 or when the cross section of axle 34 is seen, the arrangement of the source of paster inside and tagma 31a is identical (paster that is Fig. 2 is symmetrical).For the channel MOS gate device, this profile is described in Figure 11.
As a comparison, source among the paster 21b shown in Figure 3 and the arrangement of tagma 31b are asymmetric.Concrete, in paster shown in Figure 3, when in the cross section of 12-12 along the line (for the channel MOS gate device, this profile is described in Figure 12) when seeing, the arrangement of the source of paster inside and tagma 31b with when the source of the paster inside when axle 36 the cross section of Fig. 3 is seen and the arrangement different (latter's profile is identical with the profile of the paster 21a of Fig. 2 of 11-11 intercepting along the line) in tagma.
The inside sources of Fig. 2 and the geometry in tagma are shown as square, but they can be rectangle, polygon (for example, comprising hexagon or octagon), circle, maybe can for straight line and/or curve in conjunction with defined shape.Similarly, the inside sources of Fig. 3 and the geometry in tagma are rectangle shown in the figure, also can may select the shape from multiple.Though the external source among Fig. 2 and Fig. 3 two figure and tagma (being respectively element 33a and 33b) are shown as the square of openings at one side, their shape also can may be selected the shape from multiple.In a possible scheme, three inner evagination grid regions (being respectively element 35a and 35b) of Fig. 2 and Fig. 3 are removed, and keep the straight flange between grid and grid contact pad 37a, 37b.
Fig. 4-6 has described three concrete metal layers designs, and it can be used to be connected the angle of four active paster 41a-d of same electrical of patch array 43a, 43b in the device described herein and 43c inside.Certainly, those skilled in the art will recognize, other internal metallization figure also is fine in a large number.Each paster in the array all is furnished with the exposed polysilicon of at least a portion, as grid contact pad 45 (polysilicon remaining part typical case covered by dielectric layer).
Shown in concrete array in, spaced-apart by gap 46 or zanjon between paster along each axle.At least some grid contact pads of paster in the array and the one or more grid contact pads on other paster in the array carry out direct or indirect electrically contacting.Therefore, in the described array of Fig. 4, utilize " dog bone (dog-bone) " shape grid metal layer 47a, cause that the grid contact pad on the 41a and the 2nd 41b paster is electrical contact with each other in the array, and the grid contact pad on the 3rd 41c and the 4 41 d paster electrically contacts in the same manner.Among Fig. 5, utilize the grid metal layer 47b of longitudinal extension, cause that the grid contact pad on the 41a and the 2nd 41b paster electrically contacts mutually in the array, and the grid contact pad on the 3rd 41c and the 4th 41d paster electrically contacts in the same manner.Among Fig. 6, utilize H shape grid metal layer 47c, cause the grid contact pad on a 41a in the array, the 2nd 41b, the 3rd 41c and the 4th 41d paster to be electrical contact with each other.
Among each embodiment in the described internal metallization embodiment of Fig. 4-6, grid metal layer 47a-c and source and body metal layer 51 electric insulations.Preferably, this can realize by retention gap between two metal layers or zanjon 53, so that two metal layers are coplane basically, because, from this arrangement of position of making most cost effective normally.But other embodiment also is fine, and wherein, two metal layers are provided with a dielectric material with the layer that stacked arrangement separately is set to separate between two metal layers, keep electric insulation each other to guarantee them.For example, in a kind of like this embodiment, the grid contact pad can contact with the first thin metal layer, and source and tagma can contact with the second thicker a little metal layer.
Fig. 7-9 has described to pass the object lesson of the metallization scheme that may occur of four identical pasters at the outside corner of wafer.Certainly, one of skill in the art will appreciate that a large amount of other metallization scheme also have passable.Among the described array 61a of Fig. 7, terminal metal layer 70a extends through outside paster 65,66 and 67, causes the source of those pasters and tagma and grid contact pad to electrically contact.Source and body metal layer 71a extend through a part of inner paster 68.Grid metal layer 63a extends through inner paster 68, comprises grid contact pad 69a.
The array 61b of Fig. 8 is similar to the situation of Fig. 7, and different is that ' terminal metal layer 70b and source and body metal layer 71b draw closer together, and the grid contact pad 72 of inner paster 68 is by electric insulation.The array 61c of Fig. 9 and Fig. 8 difference mainly are terminal metal layer 70c and source and body metal layer 69c in shape.Once more, the grid contact pad 72 of inner paster 68 is by electric insulation.
When the design paster, some key characteristics and consideration item useful in the array of shop drawings 1-9 shown type are as follows:
1. paster is preferably dimensioned to be the length of each patch edges and widely just in time is the wide wide required size that adds the device edge terminal on each limit that appears at paster of line (the another kind of selection be, the length of patch edges and widely may be selected to be line and add that the device edge terminal that appears on each limit of paster multiply by the size of an integer).
2. be reduced to minimumly for all resistance with the contribution of source and body metal layer, preferably active and body contact is continuously and the possible width that preferably has maximum with institute for source and body metal layer.
3. the grid conductor that is used for each paster preferably comprises enough gate contacts, to provide acceptable low resistance for whole grid when metallizing.
4. the grid conductor of the paster at periphery place and source and tagma preferably provide acceptable edge termination when linking together with metal.
5. the source pad employing is called " bonding on the active area (bonding over the activearea) " technology and is preferably placed on one or more pasters or the paster part.Use this packaging technology, one or more wire bonds directly adhere to source and the bulk metal layer on source and tagma and the grid region.The use of the technology of bonding has increased and has contained the active and chip area tagma on the active area, has increased utilance, and has exempted the needs that use special-purpose " source bonding welding pad " unit in the present invention.
6. gate pads is preferably formed in the set of all pasters or paster, does not contact the source and the tagma of those pasters.
Figure 10 shows the detailed placement of the vertical DMOS device of the described type of Fig. 1.Though one group of arbitrary dimension all can be used for making vertical DMOS, concrete array 71 shown in Figure 10 is the paster 73 of 7 * 9 arrays.Certainly note that 7 * 9 arrays shown in Figure 10 only comprise the effective dimensions of 6 * 8 pasters because each paster of each edge 1/2 be arranged in adjacent device.Shown in concrete array in, gate pads 75 is positioned at place in the middle of the device bottom, source pad 77 is positioned at the device center.Select odd number paster or even number paster along each axle, influenced position, the position of gate pads and the symmetry of device of source and body pad.
Paster described herein allows to use a plurality of source pad and/or gate pads, and the bonding wire that separates can be attached on it.Produce relatively large device under the situation of the series resistance of this specific character permission in not enlarging markedly source and body metal layer or grid conductor.
So far, to having identical length and wide paster is described.But, also may use different long and wide pasters in the Apparatus and method for described herein.But based on the factor of the validity of optimizing distribution, preferably, if paster is wide and long unequal, then the longest dimension of paster is the integral multiple of short size.
Fig. 2 and the also available trench technology of the both available planar technique of paster shown in Figure 3 are made.If the employing trench technology is only forming on the surface of multi-crystal silicon area ability at wafer at gate contact 37a and 37b place.
Figure 11 and 12 shows the details of the paster of the Fig. 2 of concrete raceway groove DMOS structure and 3 described types.Figure 11 shows the profile of the unit of Fig. 2 11-11 intercepting along the line.This profile and Fig. 2 are along the profile identical (being that paster is symmetrical) of axle 34 interceptings and identical along the profile of axle 36 interceptings with Fig. 3.Figure 12 shows the profile of Fig. 3 12-12 along the line intercepting, but with profiles different (they being that paster is asymmetric) along axle 36 interceptings.Back one profile is identical with the described profile of Figure 11.
With reference to Figure 11 and 12, device described herein comprises N +Substrate 91 and epitaxial loayer 93.A series of raceway grooves 95 are formed in the epitaxial loayer.Each raceway groove is all filled doped polycrystalline silicon 97 and is comprised gate oxide layers 99.Each raceway groove is limited by double diffusion source and tagma 101 all, and wherein double diffusion source and tagma 101 comprise: source electrode 103, spread more shallow p type island region 104 and the darker P of diffusion +District 105.Source and body metal layer 107 appear on the top surface, contact with tagma 101 with the source.
As shown in table 1, wafer size is made by multirow row paster with as the single paster of gate pads.Some wafer sizes are because the depth-to-width ratio that produces is seen perhaps unengaging from making viewpoint.For example, perhaps depth-to-width ratio is not easy to create greater than 3: 1 device.Except the wafer size shown in the table 1, also can obtain greater than the wafer size shown in the table 1.The size of independent array (each array all comprises a paster as gate pads) does not have the specific upper limit, if but the wafer size growth is too big, then there is the problem on making.The minimum practical dimensions of independent array that comprises a gate pads is by the effective number of arrays decision of single gate pads array.If the independent array size below 2 * 3 pasters, does not just need to handle effective paster.Independent array size for 2 * 3, the ratio of source and consideration sheet area and grid pad paster area is 1: 1, this ratio is perhaps too little, so that impracticable in many occasions.
Table 1: the layout that is used for the paster of different size device
Interior inner paster number Interior local array size Source and consideration sheet number Grid paster number Paster sum in the horizontal direction Paster sum in the vertical direction The ratio of inner paster and total paster
2 1×2 1 1 2 3 2∶6
3 1×3 2 1 2 4 3∶8
4 2×2 3 1 3 3 4∶9
6 2×3 5 1 3 4 6∶12
8 2×4 7 1 3 5 8∶15
9 3×3 8 1 4 4 9∶16
10 2×5 9 1 3 6 10∶18
12 3×4 11 1 4 5 12∶20
15 3×5 14 1 4 6 15∶24
18 3×6 17 1 4 7 18∶28
20 4×5 19 1 5 6 20∶30
25 5×5 24 1 6 6 25∶36
30 5×6 29 1 6 7 30∶42
35 5×7 34 1 6 8 35∶48
40 5×8 39 1 6 9 40∶54
49 7×7 48 1 8 8 49∶64
64 8×8 63 1 9 9 64∶81
81 9×9 80 1 10 10 81∶100
100 10×10 99 1 11 11 100∶121
Device with previous disclosed paster manufacturing need produce contact mask, metal mask and pad mask for each new unit.Each new unit is all needed independent contact mask, and this needs can be eliminated by comprise special-purpose grid pad paster with proper spacing in subarray.The position of special-purpose grid pad paster may be selected to be each wafer one or more gate pads is provided in the subarray.In certain embodiments, these special-purpose grid pad pasters comprise identical polysilicon layer geometry, as active paster, and the occlusion body dopant, but do not have the source doping agent, and the tagma is non-ly to electrically contact.
In other embodiments, special-purpose grid pad paster comprises continuous polysilicon layer geometry, and only outer periphery mates the geometry of active paster.The body dopant appears under the polysilicon continuously, and can electricity floats or be electrically connected to source and body end.Can adopt various other polysilicon geometry and dopant location, obtaining and the electrically contacting of grid, and not influence the electrical property of paster or significantly increase the conducting resistance of device.
Grid pad paster can be positioned over horizontal direction also can be positioned over vertical direction, and the number of the effective paster between them both can be odd number and also can be even number.If, just can obtain bigger symmetry along between the grid pad paster of each, selecting odd number.The definite number of the effective paster between the grid pad paster on each direction has determined to be used for the wafer size of allowing of same wafer.For example, in the device 111 of Figure 13,5 effective paster 115a are arranged between grid pad paster 113a on the horizontal direction, and 7 effective pasters are arranged in vertical direction.In whole subarray 117a, calculate all row and columns, comprise 6 row and 8 row.
Available many subarrays design device, and each subarray all comprises a grid pad paster.In the example shown in Figure 13-15,, show obtainable three typical wafer sizes and three possible subarray layout 117a, 117b and 117c for one 5 * 7 subarray.Therefore, Figure 13 has described the device that comprises 3 * 3 subarray 117a.Figure 14 has described 1 * 2 orientation 119 of subarray, and Figure 15 has described 2 * 3 orientations 121 of subarray.Table 2 has proved other the possible device that is made of subarray shown in Figure 15.
Table 2: the subarray layout that each all has special-purpose grid pad and comprises 6 * 8 pasters
The submatrix columns The subarray orientation Paster number on the horizontal direction Paster number on the vertical direction Effectively paster and the always ratio of paster Depth-to-width ratio
1 1×1 6 8 34∶48 3∶4
2 1×2 6 16 73∶96 3∶8
2 2×1 12 8 75∶96 3∶2
3 1×3 6 24 112∶144 1∶4
3 3×1 18 8 116∶144 9∶4
4 1×4 6 32 151∶192 3∶16
4 2×2 12 16 161∶192 3∶4
4 4×1 24 8 157∶192 3∶1
5 1×5 6 40 190∶240 3∶20
5 5×1 30 8 198∶240 15∶4
6 1×6 6 48 229∶288 1∶6
6 2×3 12 24 247∶288 1∶2
6 3×2 18 16 249∶288 9∶8
6 6×1 36 8 239∶288 9∶2
7 1×7 6 56 268∶336 3∶28
7 7×1 42 8 280∶336 21∶4
8 1×8 6 64 307∶384 3∶32
8 2×4 12 32 333∶384 3∶8
8 4×2 24 16 337∶384 3∶2
8 8×1 48 8 321∶384 6∶1
9 1×9 6 72 346∶432 1∶12
9 3×3 18 24 382∶432 3∶4
9 9×1 54 8 362∶432 27∶4
If want to obtain required puncture voltage, the use of patch array proposes some special requirements to patch design, and patch array can be provided with in manufacturing process afterwards, to produce the mos gate device of different size.These requirements cause the following guilding principle that is used for the paster layout:
1. the source of each paster and tagma should be separated with the source and the tagma of other all pasters.
2. the grid of each paster should be separated with the grid of other all pasters.
3. when paster and terminal suitably metallized, single metallization paster should be able to bear required puncture voltage.
4. when paster and terminal suitably metallized, many pasters should be able to bear required puncture voltage.
5. when the grid region on the paster that is electrically connected to those neighborings that form line and edge termination, the combination of source diffusion and body diffusion should be able to be born required puncture voltage.
These guilding principles are applicable to the patch design of any uniqueness, to obtain required puncture voltage.The device made from particular technology is described below.
Plane mos gate device with those grid structure manufacturings shown in Fig. 2-3 needs terminal structure.As above-mentioned discussion, the geometry of each paster must be followed 5 guilding principles, simultaneously break-over of device resistance is reduced to minimum.Available semi-conducting material with lowest impedance obtains maximum puncture voltage, utilizes this method to minimize break-over of device resistance.Require to optimize paster terminal structure and manufacturing process.
Terminal structure 131a-d shown in Figure 16-19 can use together with low pressure, plane mos gate device.Each structure comprises polysilicon gate 133, and it is encapsulated in the dielectric layer 135 and is positioned in source 137 and body 139 districts.Shown in certain device in, the tagma is made of more shallow diffusion region 141 and darker diffusion region 143.Metal layer 145 extends through the surface of device, provides and the contacting of diffusion region.If the periphery knot is not an active junction, then can float by electricity in the grid region of adjacent perimeter, if but periphery is become active junction, then must be electrically connected continuous with grid.
Example shown in Figure 16-19 is not giving an example of a limit, but it has embodied available exemplary terminal technology.The terminal structure that employing comprises active junction has increased the electric current that flows through device, and the area of paster increases on a small quantity.This Active Terminal structure return the device contribute current, and the passive termination structure only can be born puncture voltage except bearing puncture voltage.
Channel MOS gate device shown in Figure 11-12 also comprises many different the paster layout and manufacturing process that can produce required puncture voltage.The example of the terminal structure 151a-d that generates is shown in Figure 20-23.As shown here, each structure comprises a series of raceway grooves 153, and it is formed in the epitaxial loayer 155 of device.Each raceway groove is filled with doped polycrystalline silicon 157, and comprises gate oxide layers 159.Each raceway groove is limited by double diffusion source and tagma 161, and it can be by diffusion more shallow p type island region 163 and the darker P of diffusion +District 165 constitutes.N + Doping source region 167 is positioned at the raceway groove top, and also can electrically contact with metal layer 169.The modification of various these terminal structures and other terminal structure can be used for around each paster, to optimize specific conducting resistance.The same with plane terminal, if the periphery knot is not active, then can float by electricity in the grid region of adjacent perimeter, if active but periphery is become, then this grid region must be electrically connected continuous with grid.
Though describe and described various embodiment, one of skill in the art will appreciate that under the situation that does not depart from spirit of the present invention and desired extent, modification of the present invention and variation are contained in above-mentioned instruction and locate within the scope of the appended claims herein.And these examples should not be understood that to limit the modifications and variations of the present invention that claim contains, and contingent variation only has been described.

Claims (14)

1. method of making the mos gate device may further comprise the steps:
A plurality of discontinuous pasters are provided, and each paster in described a plurality of discontinuous pasters has at least one source region and at least one tagma; And
Paster is assembled into array, so that form the mos gate device,
Wherein, along line by each outer periphery paster center, cutting forms the paster of device outer periphery, make the size of paster at each outer periphery turning be not positioned at the paster on the device outer periphery size 1/4th, and the size of the paster on each outer periphery sideline is half of size that is not positioned at the paster on the device outer periphery.
2. the method for claim 1, wherein a plurality of pasters are identical.
3. each paster in the method for claim 1, wherein a plurality of pasters is a rectangle.
4. each paster in the method for claim 1, wherein a plurality of pasters is a square.
5. the method for claim 1, wherein each paster all has a plurality of provided thereon a plurality of gate contact zones.
6. method as claimed in claim 5, wherein, each paster is a rectangle, and wherein, each angle of each paster all has provided thereon gate contact zone.
7. method as claimed in claim 5, wherein, each paster is a square, and wherein, each angle of each paster all has provided thereon gate contact zone.
8. the method for claim 1, wherein each paster comprises multiple source and tagma, and wherein, multiple source and tagma are arranged in the subarray.
9. the method for claim 1, wherein described array also comprises the grid metal layer.
10. the method for claim 1, wherein described array also comprises source and body metal layer.
11. the method for claim 1, wherein described array also comprises grid metal layer and source and body metal layer, and wherein, grid metal layer and source and body metal layer are electrically insulated from each other.
12. at least some pasters in the method for claim 1, wherein described a plurality of discontinuous paster comprise the epitaxial loayer that wherein is provided with at least one raceway groove, and wherein, are provided with the part doped polycrystalline silicon in described at least one raceway groove.
13. at least one paster in the method for claim 1, wherein described a plurality of discontinuous paster comprises grid structure.
14. method as claimed in claim 13, wherein, the part of grid pole structure is that electricity floats.
CNB038106094A 2002-05-10 2003-05-09 Surface geometry for a MOS-gated device Expired - Fee Related CN100530568C (en)

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