JP2024511470A - Power MOSFET shield contact layout - Google Patents

Abstract

The method includes defining a first type of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) extending vertically in a semiconductor substrate, and defining a second type of trenches (105, 105-1, 105-2, 105-3, 105-4) extending laterally and intersecting the first type of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U). The second type of trench (105, 105-1, 105-2, 105-3, 105-4) is in fluid communication with each of the plurality of intersecting trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type. The method further includes disposing a shield poly layer (111) within the plurality of trenches of the first type (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the plurality of trenches of the second type (105, 105-1, 105-2, 105-3, 105-4); and disposing an interpoly dielectric layer (112) and a gate poly layer (108) over the shield poly layer (111) in the first type trenches (105, 105-1, 105-2, 105-3, 105-4) and the second type trenches (105, 105-1, 105-2, 105-3, 105-4), and forming electrical contacts to the shield poly layer (111) through the openings (106, 16) in the interpoly dielectric layer (112) and the gate poly layer (108) disposed in the second type trenches.

Description

(Cross reference to related applications)
This application is filed under U.S. Provisional Application No. 17/655, filed March 21, 2022, which claims priority to and benefits from U.S. Provisional Patent Application No. 63/166,242, filed March 26, 2021. , 579, which is incorporated herein by reference in its entirety.

This application claims priority to and benefits from U.S. Provisional Patent Application No. 63/166,242, filed March 26, 2021, which is incorporated herein by reference in its entirety.

(Field of invention)
This description relates to contacts in shielded gate trench MOSFETs.

A buried polysilicon shield electrode is used in shield gate trench MOSFETs to balance charge and reduce the drain-source on resistance (RDS _on ) of the device. However, the resistance and stray capacitance associated with the polysilicon shield electrode can reduce the electrical power of the device by, for example, causing undesirable gate bounce or poor avalanche capability during unclamped inductive switching (UIS) in the device circuit. performance or application efficiency. As semiconductor devices (e.g., device cell dimensions) and lithography design rules shrink, lower resistance is introduced into semiconductor devices (e.g., shielded gate trench MOSFETs) to avoid or reduce gate bounce and poor avalanche capability, for example. It becomes increasingly difficult to make buried polysilicon shield electrodes.

In a general aspect, a device includes a plurality of trenches of a first direction type extending longitudinally in a semiconductor substrate and a plurality of trenches extending transversely and intersecting a plurality of trenches of a first direction type in a semiconductor substrate. and a second direction type trench. The longitudinal direction is perpendicular to the transverse direction. The second directional type trench is in fluid communication with each of the plurality of intersecting trenches of the first directional type.

The device includes a shielding poly layer disposed within the plurality of trenches of the first orientation type and the trenches of the second orientation type, and a shielding poly layer disposed within the plurality of trenches of the first orientation type and the trenches of the second orientation type. an inter-poly dielectric layer (IPL) and gate poly layer disposed above the poly layer and within the opening of the inter-poly dielectric layer (IPL) and gate poly layer disposed within a second direction type trench; and an electrical contact to the shield poly layer disposed on the shield poly layer.

In a general aspect, the device includes a plurality of longitudinal trenches and mesas of a first directional type extending parallel to the longitudinal direction across a semiconductor substrate and a plurality of longitudinal mesas of a first directional type extending in a transverse direction perpendicular to the longitudinal direction. a plurality of vertical trenches of one directional type and horizontal trenches of a second directional type perpendicularly intersecting the vertical mesa. The lateral trenches are in fluid communication with the plurality of vertical trenches of the first directional type. The horizontal trench includes a first section vertical trench and a first section mesa on a first side of the horizontal trench, and a second section mesa on the opposite side of the first side of the horizontal trench. A lateral trench is in fluid communication with each of the plurality of first section longitudinal trenches and second section longitudinal trenches.

The device includes a shielding poly layer disposed within the plurality of vertical trenches and horizontal trenches, and an interpoly dielectric layer (IPL) and gate poly layer disposed over the shielding poly layer within the plurality of vertical trenches and horizontal trenches. , an electrical contact to the shield poly layer by at least one insulator covered conductive plug extending through the interpoly dielectric layer and the gate poly layer disposed within the lateral trench.

In a general aspect, a method includes defining a plurality of trenches of a first type in a semiconductor substrate. The plurality of trenches of the first type extend longitudinally. The method further includes defining a second type of trench that extends laterally and intersects the plurality of trenches of the first type. The second type of trench is in fluid communication with each of the first type of intersecting trenches. The method includes placing a shielding poly layer within a plurality of trenches of a first type and a trench of a second type; disposing an interpoly dielectric layer (IPD) and a gate poly layer thereon and providing electrical connection to the shield poly layer through openings in the interpoly dielectric layer and gate poly layer disposed in a second type of trench. forming a contact.

3 illustrates a portion of an example device mask layout. 1 illustrates a portion of an exemplary shielded gate trench MOSFET device. 2B is an exemplary cross-sectional view of a portion of the device of FIG. 2A; FIG. 2B is an exemplary illustration of another cross-sectional view of a portion of the device of FIG. 2A; FIG. 2 illustrates another example shielded gate trench MOSFET device. FIG. 3 is an illustration of yet another exemplary shielded gate trench MOSFET device. FIG. 3 is an illustration of a further exemplary shielded gate trench MOSFET device. FIG. 3 is an illustration of yet another exemplary shielded gate trench MOSFET device. FIG. 3 is an illustration of an additional example shielded gate trench MOSFET device. FIG. 3 is an illustration of yet another additional exemplary shielded gate trench MOSFET device. FIG. 2 is an illustration of an example method.

Metal oxide semiconductor field effect transistor (MOSFET) devices are used in many power switching applications. In a typical MOSFET device, a gate electrode provides turn-on and turn-off control of the device in response to an applied gate voltage. For example, in an N-type enhancement mode MOSFET, turn-on occurs when a conductive N-type inversion layer (i.e., channel region) is formed in the p-type body region in response to a positive gate voltage that exceeds a unique threshold voltage. . The inversion layer connects the N-type source region to the N-type drain region and allows majority carrier conduction between these regions.

In a trench MOSFET device, the gate electrode is formed in a trench that extends downwardly (e.g., vertically downward) from a major surface of a semiconductor material (which may also be referred to as a semiconductor region), such as silicon. Additionally, a shield electrode may be formed below the gate electrode within the trench (and may be isolated via an interelectrode or interpoly dielectric). Current flow in trench MOSFET devices is primarily vertical (eg, in the N-doped drift region), allowing for higher density packing of device cells. A device cell can include, for example, a trench containing a gate electrode and a shield electrode and an adjacent mesa containing a drain region, source region, body region, and channel region of the device.

The current handling capability of a trench MOSFET device is determined by its gate channel width. To minimize cost, we keep the transistor die area size as small as possible and increase the width of the channel surface area by creating cell structures that repeat across the entire area of the MOSFET die (i.e., "channel density"). ) may be important. A way to increase channel density (and thus increase channel width) is to reduce the size of the device cells and implement more device cells with a smaller pitch within a given surface area.

An exemplary trench MOSFET device may include an array of hundreds or thousands of device cells, each including a trench and an adjacent mesa. Device cells may be referred to herein as trench-mesa cells because each device cell geometrically includes a trench and a mesa (or two half-mesa) structure. The shield and gate electrodes may be formed inside a linear trench (eg, trench 101) extending along (eg, aligned with) a mesa (eg, mesa 102). The shield and gate electrodes are fabricated from polysilicon (e.g., "n+ shield polysilicon" and "n+ gate polysilicon") and are fabricated from a dielectric layer (e.g., inter-poly dielectric (IPD) layer 112). , FIG. 2B). The IPD layer may be, for example, an oxide layer. The shield and gate electrodes are also separated from the silicon in the mesa by dielectric layers (eg, a shield dielectric and a gate dielectric layer).

To ensure proper electrical contact of all cells, a "planar stripe" structure is often used for trench MOSFETs fabricated on the semiconductor die surface. In a planar stripe structure, the gate electrode ("gate") and shield electrode ("shield poly") in the trench (e.g., linear trench) extend (e.g., are aligned) along the length of the trench in the vertical stripe. It is arranged like this. A trench containing a gate electrode and a shield electrode can be referred to as an active trench; the gate electrode (e.g., made of gate poly) is connected along the length of the active trench with the shield electrode (e.g., made of shield poly). ) is placed above (or above). The gate poly in the active trench is exposed and contacted at the stripe ends by gate runners (e.g. gate metal), and the shield electrode (shield poly) in the trench is exposed and contacted at the stripe ends by gate runners (e.g. gate metal), and the shield electrode (shield poly) in the trench is exposed and contacted at the stripe edges by the source metal. can be exposed at locations along and lifted to the surface (using a masking step).

In modern trench MOSFET devices (eg, those with narrow linewidths), shield resistance is a factor that affects the efficiency and performance of the device. Lower shield resistance can be achieved by making multiple contacts to the shield poly in the active trench (e.g., passing the shield poly through the gate poly to the surface in multiple locations to make multiple shield contacts with the source metal). by lifting it vertically).

By lifting the shield poly perpendicular to the surface (from just below the gate poly), the continuity of the gate poly along the length of the active trench is interrupted or destroyed. The gate poly is divided into two discrete segments along the length of the active trench by each instance of shield poly raised perpendicular to the surface. In an exemplary implementation, two separate gate runners or gate metal strips at the ends of the stripes (e.g., gate metal 710-1, 710-2 shown in FIGS. 6 and 7) run through the active trenches. It may be necessary to contact two discontinuous gate poly segments created by a single instance of shield poly raised perpendicular to the surface. Multiple instances of shield poly that are pulled vertically up to the surface through the gate poly along the length of the active trench result in several isolated gate poly segments that become floating (i.e. two separate gate runners). Therefore, multiple gate runners are required to contact each gate poly segment, which takes up die area.

This disclosure describes example device configurations or layouts for making contacts to a shield electrode buried beneath a gate electrode in an active trench of a MOSFET device fabricated in a semiconductor substrate. Contacts (e.g., metal, metal alloy, metal silicide, conductive poly, or other conductive material contacts) to the shield poly buried below the gate poly in the shield connection trench perpendicular to and across the active trench. It is made by The shield connection trench may be a side trench portion of the active trench. The contacts were covered with vertical insulators extending from the top surface through the gate poly (and other dielectric, e.g. interlayer dielectric) overlaid on the shield electrode to reach the buried shield poly (e.g. through an opening (covered with oxide). The buried shield poly is left in place below the gate poly and is not lifted to the surface. Alternatively, contacts to the shield poly are made by depositing a conductive material (eg, metal, tungsten) within the opening. The gate poly is routed in a horizontal plane around the opening in the shield connection trench to connect the gate electrode in a portion of the active trench on one side of the contact and a corresponding portion of the active trench on the opposite side of the contact. Maintain continuity.

FIG. 1 shows a portion of an exemplary device mask layout 100 for a shield gate trench MOSFET device (e.g., device 200 of FIGS. 2A, 2B, and 2C), in which multiple contacts can be made. FIG. 1 shows, for example, a device mask layout 100 in the xy plane (the xy plane can be aligned along the plane of a silicon wafer or semiconductor substrate of a transistor device).

For convenience of explanation, the relative orientations or coordinates of the features of the disclosed trench MOSFET devices (e.g., trenches 101 and 105, mesa 102, etc.) are herein referred to as the x-axis and It may be explained with reference to the y-axis. The direction perpendicular to the xy plane of the page (eg, the z-axis) is sometimes referred to as the vertical direction or axis. The z-direction can be directed down the depth of the semiconductor substrate and can be aligned, for example, with the depth of a trench in a MOSFET device fabricated within the semiconductor substrate. Additionally, for visual clarity, a limited number of trenches/device cells (e.g., 3 to 5 trenches/device cells) of the array of trenches/device cells in device mask layout 100 are shown in FIG. It is shown. As previously mentioned, an actual MOSFET device can include an array of hundreds or thousands of trenches/device cells, which may be smaller than the limited array shown in example device mask layout 100, for example. It can be obtained by repeating the structure (eg in the x direction).

Device mask layout 100 includes several active trenches (ie, vertical trenches 101) of the device that extend parallel (eg, substantially parallel) to each other (eg, in the y direction), as shown in FIG. 1 . Mesas 102 may be formed between pairs of vertical trenches 101. Trench 101 and mesa 102 may be a linear trench and a linear mesa (eg, extending in the y direction), respectively. The trench 101 and the mesa 102 may have uniform widths Wt and Wm (eg, horizontal width in the x direction), respectively. Device elements (eg, source and body regions (not shown)) may be formed within mesa 102 and may be contacted by source metal (not shown), eg, at source contact region 103. Device elements (eg, source and body regions) may be formed, for example, by n-type source and drain (NSD) implants within section 104 of device mask layout 100.

Although only a small number of trenches 101 and mesas 102 (e.g., four trenches and three mesas) are shown in FIG. 1 (and other figures herein), an actual MOSFET device may contain hundreds of It should be noted that an array of several thousand trenches/device cells may be included, e.g. by repeating (e.g. in the x direction) the trench and mesa structure or pattern shown in the figure. Obtainable.

A horizontal or lateral trench (e.g., shield connection trench 105) (side trench) extends laterally (e.g., in the x direction) to intercept trench 101 and mesa 102 at a distance Y along the y-axis. , can be traversed (i.e., traversed). For example, the shield connection trench 105 may have a vertical width Wv in the y direction. The shield connection trench 105 may effectively divide each vertical trench 101 and each mesa 102 into two sections (e.g., the upper region of the device mask layout 100 above the shield connection trench 105 in the y direction (e.g., region 10U). ) in the upper section of the vertical trench 101 in the y-direction, and in the lower section of the trench 101 in the lower region of the device mask layout 100 (eg, region 10L) below the shield connection trench 105 in the y direction). The trenches (ie, trench 101 and trench 105) may have approximately the same depth (not shown), for example, referenced from the top surface of mesa 102.

In an exemplary implementation, two sections of vertical trench 101 above shield connection trench 105 on either side (i.e., upper and lower) (i.e., an upper section of vertical trench 101 in upper region 10U, and a lower (lower section of the corresponding trench 101 in region 10L) may be aligned in the horizontal x-direction (i.e., share a common y-axis Yt, as illustrated in FIG. 1 for the second vertical trench from the right of the page). (or place it on top of it).

Shield connection trench 105 is in fluid communication with each of the divided sections of trench 101 (in other words, shield connection trench 105 has a physical opening in each of the divided sections of trench 101 so that fluid ( That is, a gas or liquid (with a non-fixed shape) can easily flow through the openings into each of the divided sections from the shield connection trench 105 to the trench 101, and vice versa). Shield and gate electrodes (not shown) of the device can be formed in trench 101, for example, by depositing shield poly and gate poly in trenches 101 and 105. The shield poly and gate poly may be separated by an interpoly dielectric (IPD) layer (not shown in FIG. 1).

The shield poly in shield connection trench 105 has one or more openings made from the top surface of the gate poly (through the gate poly and IPD layer in shield connection trench 105 to reach the underlying shield poly). For example, a conductive plug covered with an insulator (e.g., at least FIGS. 2A, 2B, An insulator-covered conductive plug 116 shown in FIG. 2C and an insulator-covered conductive plug 116 may be fabricated within the opening 106. A conductive central portion made of conductive material 109 (FIG. 2A) surrounded by concentric insulating outer portions (fabricated) can include a conductive central portion made of conductive material 109 (FIG. 2A) surrounded by concentric insulating outer portions.

In an example implementation, referring again to device mask layout 100 (FIG. 1), opening 106 may first be filled with an oxide (e.g., oxide 110, FIG. 2A) or other insulator. , another opening is then made through the oxide or other insulator filling to form an insulator-covered opening (e.g., opening 16) to connect the underlying shield. You may reach poly again. In the device mask layout 100 shown in FIG. 1, this additional insulator-covered opening (i.e., opening 16) is shown as a dashed rectangle within opening 106.

A metal or other electrically conductive material (e.g., electrically conductive material 109, FIG. 2A) is connected to an underlying shield, for example, for connection with a source metal of the device (e.g., source metal 720, FIGS. 6-9). Oxide can be deposited within the oxide-covered opening 16 to establish electrical contact with the poly.

In an exemplary implementation, the gate poly deposited within the shield connection trench 105 along the sides or perimeter of the insulator-covered conductive plug 116 formed within the opening 106 is removed from the shield connection trench 105. (in other words, the gate poly of a section of trench 101 in upper region 10U is similar to the gate poly of a corresponding section of trench 101 in lower region 10U). continuous).

In example implementations, openings 106 and 16 (and insulator-covered conductive plug 116) have a square, rectangular, circular, oval, or any other shape in the xy plane. Can be done. In an exemplary implementation, as shown in FIG. 1, the opening 106 can have, for example, a rectangular shape with a width Wo in the x direction and a length Lo in the y direction. In exemplary implementations, the width Wo may be greater than, the same as, or less than the width Wm of mesa 102.

In an exemplary implementation, for a MOSFET with a breakdown voltage BVDSS of 25V to 30V, trench 101 may have a width Wt in the range of approximately 0.2μm to 1.0μm (eg, 0.3μm), for example. , mesa 102 can have a width Wm in the range of about 0.2 μm to 1.0 μm (eg, 0.3 μm), and shield contact trench 105 can have a width Wm in the range of about 0.5 μm to 2.0 μm, for example. The insulator-covered conductive plug 116 may have a width Wv of approximately 0.3 μm to 2.0 μm (eg, 1.4 μm), The contact opening 16 can have a length Lo in the range of about 0.3 μm to 1.2 μm (eg, 0.6 μm), and the contact opening 16 can have a length Lo in the range of about 0.1 μm to 1.8 μm (eg, 1.0 μm). ) and a length in the y direction of about 0.1 μm to 1.0 μm (eg, 0.2 μm).

For MOSFETs with a breakdown voltage BVDSS greater than 30 V, the dimensions of the aforementioned features are (e.g., width Wt of trench 101, width Wm of mesa 102, width Wv of shield contact trench 105, conductive The width Wo and length Lo of the plug 116 and the width and length Lo of the contact opening 16 can be larger than the values in the example above for a MOSFET with a breakdown voltage BVDSS of 25V to 30V.

In an exemplary implementation, several arrays of openings 106 (e.g., array 106A) are connected to the shield to form a corresponding array 116A (FIG. 2A) of insulator-covered conductive plugs 116. It may be located along the x-axis within trench 105.

In an exemplary implementation, as shown in FIG. 2A, the insulator-covered conductive plug 116 in the shield connection trench 105 connects the mesa 102 of the upper region 10U and the corresponding mesa 102 of the lower region 10L in the y direction. (in other words, each insulator-covered conductive plug 116, the mesa 102 of the upper region 10U, and the corresponding mesa 102 of the lower region 10L can all be aligned with a common axis in the y direction (e.g., FIG. 2A may be placed along the axis Ym).

FIG. 2A shows an exemplary shield gate trench MOSFET device 200 with a gate electrode that is continuous around the perimeter and uninterrupted (i.e., uninterrupted) by a shield contact made to the shield poly below the gate electrode. . In an example implementation, device 200 may be fabricated using device mask layout 100, for example. In the example shown in FIG. 2A, device 200 includes an active trench 101 and mesa 102 extending in the y direction, and a horizontal shield connection trench 105 (e.g., extending laterally (e.g., in the x direction) across trench 101 and mesa 102). side trench). Corresponding sections of active trench 101 (and mesas 102) extending in the y direction above and below horizontal shield connection trench 105 may be aligned with each other in the x direction (in other words, sections of trench 101 above and , the corresponding sections of trench 101 below may share a common y-axis (eg, axis Yt) and may not be offset from each other in the x-direction). FIG. 2A, for example, shows a section 101-U of trench 101 above and a corresponding section 101-L of trench 101 below horizontal shield connection trench 105 aligned on a common y-axis (ie, Yt). Similarly, adjacent sections of mesa 102 above and below horizontal shield connection trench 105 are aligned on a common y-axis (ie, Ym).

In an exemplary implementation, the gate poly deposited in the shield connection trench 105 along the sides or perimeter of the insulator-covered conductive plug 116 is connected to the gate electrode in the trench 101 across the shield connection trench 105. (In other words, the gate poly of a section of the trench 101 in the upper region 10U is continuous with the gate poly of the corresponding section of the trench 101 in the lower region 10U through the shield connection trench 105. are doing).

Gate oxide 107 may be grown or deposited on the sidewalls of mesa 102 adjacent active trench 101 and shield connection trench 105. A layer of gate poly 108 is deposited within active trench 101 and shield connection trench 105, overlaying the shield poly (shield poly layer 111, FIG. 2B) and interpoly dielectric (IPD) layer 112 previously deposited within the trench (FIG. 2B). A gate electrode may be formed on top of the IPD layer 112 (FIG. 2B). The layer of shield poly and the layer of IPD are buried under the gate poly 108 and are therefore not visible in FIG. 2A.

In device 200, the buried shield poly layer is contacted by an array (e.g., array 116A) of conductive plugs 116 (e.g., array 116A) covered with vertical insulators fabricated through the layers of gate poly 108 and IPD 112 in shield connection trenches 105. be done. Each insulator-covered conductive plug 116 may include a conductive central portion surrounded by an insulating liner. In an exemplary implementation, the insulating liner may be made from an insulating material such as oxide 110 and the conductive central portion may be made from conductive material 109 (eg, tungsten). The conductive material 109 (eg, tungsten) of each insulator-covered conductive plug may electrically contact gate poly 108 and shield poly buried beneath IPD layer 112 within device 200 . The gate poly 108 along and around the vertical insulator covered conductive plug 116 can maintain electrical continuity of the gate electrode formed in the active trench 101 across the shield connection trench 105. .

Electrical contacts to the buried shield poly layer are covered with at least one insulator that penetrates the interpoly dielectric layer 112 and the gate poly layer 108 located within the shield connection trench 105 to reach the buried shield poly layer. A conductive plug 116 is used.

In an exemplary implementation, the number of vertical insulator covered conductive plugs 116 in shield connection trench 105 is equal to the number of active trenches 101 (or mesas 102) intersected by shield connection trench 105 (or approximately equal). Further, in the exemplary implementation, each insulator-covered conductive plug 116 has a section of mesa 102 in upper region 10A and a corresponding section of mesa 102 in lower region 10L, as shown in FIG. 2A. It can be placed in the space between. The conductive plug 116 covered with each insulator can have a rectangular shape having a width Wo in the x direction and a length Lo in the y direction. In example implementations, the width Wo may be greater than, the same as, or less than the width Wm of mesa 102, as described above. For example, in the exemplary implementation shown in FIG. 2A, width Wo may be approximately two to three times as large as length Lo.

2B and 2C show cross-sectional views of a portion of device 200. FIG. 2B shows, for example, a portion of a section of mesa 102 in upper region 10A, a portion of a corresponding section of mesa 102 in lower region 10L, shield connection trench 105, and conductive plug 116 covered with an insulator (mesa 102). 2A (taken in the zy plane along line AA in FIG. 2A). Insulator-covered conductive plug 116 includes a conductive central portion (eg, conductive material 109) surrounded by a concentric insulating outer portion (eg, oxide 110). FIG. 2B shows an insulator-covered conductive plug 116 passing through the gate poly 108 and IPD 112 to the buried shield poly layer 111 in the shield connection trench 105. A conductive material 109 (eg, tungsten) in the conductive central portion of the insulator-covered conductive plug 116 electrically contacts the buried shield poly layer 111 within the shield connection trench 105 . Buried shield poly layer 111 may be isolated from the bottom and sides of shield connection trench 105 by a dielectric layer (eg, oxide layer 113).

FIG. 2C shows, for example, a cross-sectional view (taken in the z-x plane along line BB in FIG. ). FIG. 2C shows, for example, two insulator-covered conductive plugs 116 passing through gate poly 108 and IPD 112 to reach buried shield poly layer 111 in shield connection trench 105. FIG. Similar to FIG. 2B, each of the two insulator-covered conductive plugs 116 includes a conductive central portion (e.g., conductive material 110) surrounded by a concentric insulating outer portion (e.g., oxide 110). 109). A conductive material 109 (eg, tungsten) electrically contacts buried shield poly layer 111 within shield connection trench 105.

As previously mentioned, in the exemplary implementation shown in FIG. 2A, the corresponding sections of active trenches 101 (and mesas 102) that extend in the y direction above and below horizontal shield connection trenches 105 extend in the x direction. aligned with each other and not offset with respect to each other in the x direction. The intersection of the shield connection trench 105 and the vertical trench 101 with unstaggered sections can create a four-way (xy) crossing of the trenches, as depicted by arrow 11 in FIG. 2A.

FIG. 3 shows another exemplary structure having a gate electrode that is continuous at the periphery and uninterrupted (e.g., non-interrupted) by a shield contact made to the shield poly under the gate electrode in a horizontal shield connection trench. A shield gate trench MOSFET device 300 is shown. In device 300, corresponding sections of active trenches 101 (and mesas 102) extending in the y direction above and below horizontal shield connection trenches 105 are offset relative to each other in the x direction, for example by a distance DS in the x direction. ing. Shield connection trench 105 may serve as a termination trench for staggered sections of vertical trench 101, and may serve as a three-way (x-x-y) cross-section of the trench, as depicted by arrows 12 in FIG. may be generated. Processing a three-way cross of trenches may be preferable to processing a four-way cross of trenches (arrow 11 in FIG. 2A) under some processing conditions.

4 and 5 show other exemplary shielded gate trenches having gate electrodes that are continuous at the periphery and uninterrupted by shield contacts made to the shield poly below the gate electrodes in horizontal shield connection trenches. MOSFET devices (ie, device 400 and device 500, respectively) are shown. In devices 400 and 500, similar to device 200, corresponding sections of active trenches 101 (and mesas 102) extending in the y direction above and below horizontal shield connection trenches 105 are aligned with each other in the x direction; not offset relative to each other in the x direction. However, the number of vertical insulator covered conductive plugs 116 in the shield connection trench 105 may be less than the number of active trenches 101 (or mesas 102) intersected by the shield connection trench 105.

In an exemplary implementation, the number of vertical insulator covered conductive plugs 116 in the shield connection trench 105 is equal to approximately half the number of active trenches 101 (or mesas 102) that the shield connection trench 105 intersects. It's okay.

In the exemplary implementation (device 400) shown in FIG. Wo can be about twice as large as Wm). In example implementations, Wo may be approximately equal to or greater than the sum of the width of mesa 102 (Wm) and the width of trench 101 (Wt). Additionally, in the exemplary implementation, each insulator-covered conductive plug 116 includes a section of the pair of mesas 102 in the upper region 10U and a pair of mesas in the lower region 10L, as shown in FIG. The shield connection trench 105 may be located within a space between a corresponding pair of sections 102 . The conductive plug 116 covered with each insulator can have a rectangular shape having a width Wo in the x direction and a length Lo in the y direction. In an exemplary implementation, the width Wo may be greater than the width Wm of mesa 102, as described above. For example, in the exemplary implementation shown in FIG. 4, the width Wo may be approximately equal to the width of the two mesas (2Wm) and the width of the trench (Wt), i.e., Wo is approximately equal to 2*Wm+Wt. It's okay.

FIG. 5 shows another exemplary implementation of a device in which the number of vertical contact insulator-covered conductive plugs 116 in shield connection trenches 105 is equal to approximately half the number of active trenches 101 in device 500. , each insulator-covered conductive plug 116 may have a width Wo (in the x direction) smaller than the width Wm of the mesa 102. Additionally, in the exemplary implementation, each insulator-covered conductive plug 116 includes sections of alternating mesas 102 in upper region 10A and alternating mesas 102 in lower region 10L, as shown in FIG. may be located within the shield connection trench 105 in the space between the corresponding section of the shield. In other words, for the first mesa 102, the conductive plug covered with the aperture insulator is connected to the section of the first mesa 102 in the upper region 10U and the corresponding section of the first mesa 102 in the lower region 10L. However, with respect to the second (adjacent) mesa 102, the insulator-covered conductive plug 116 may be located within the shield connection trench 105 in the space between the upper section of the second mesa 102. and the bottom section.

In the examples shown in FIGS. 1-5, vertical active trenches and mesas (e.g., trenches 101 and mesas 102) extend vertically (e.g., along the y-axis or y-direction) from the gate contact region (gate feed). Exists. Vertical active trenches and mesas may extend, for example, between two gate feeds (eg, gate metal 710-1 and gate metal 710-2 in FIGS. 6-8). The plurality of vertical active trenches and mesas may, for example, be vertically traversed by a single horizontal shield connection trench 105, with a single insulator-covered conductive plug disposed within the shield connection trench 105. A linear array (eg, array 116A) is used to make shield contacts to the shield poly within the device.

6, 7, 8, and 9 illustrate vertical active trenches and mesas (eg, trenches) between two gate feeds (eg, gate metals 710-1 and 710-2 in FIGS. 6-8). 101 and mesa 102) are vertically traversed by two or more horizontal shield connection trenches, using two or more linear arrays (e.g., array 116A) of conductive plugs covered with an insulator (e.g., array 116A). FIG. 7 shows another exemplary implementation in which shield contacts can be formed to shield poly in horizontal shield connection trenches of FIG.

FIG. 6 shows another exemplary shield gate trench MOSFET device 600 having a gate electrode that is continuous around the perimeter and uninterrupted by shield contacts made to the shield poly below the gate electrode. In the example shown in FIG. 6, the device 600 includes an active trench 101 and a mesa 102 of a first direction type that extend parallel to each other in the vertical direction (eg, along the y direction) between two gate feeds. The two gate feeds include two sheets or strips of gate metal (e.g., gate metal 710-1 and gate metal 710-2) connected to a gate electrode contact (e.g., contact 702) in the end region of active trench 101. formed by.

A first horizontal shield connection trench 105-1 (side trench) of the second direction type extends laterally in the transverse direction (e.g., along the x direction) and near location Y1 on the y axis. It intersects with trench 101 and mesa 102. The second horizontal shield connection trench 105-1 (side trench) of the second direction type extends laterally in a transverse direction perpendicular to the longitudinal direction (e.g., along the x direction) and extends along the y axis. It intersects with trench 101 and mesa 102 near position Y2. Shield connection trenches 105-1 and 105-2 can effectively divide each vertical trench 101 and each mesa 102 into three sections (e.g., on the side of shield connection trench 105-1 (in the y direction) The first section of the vertical trench 101 in the first region (for example, the upper region 10U) of the sides (from the side close to the trench 105-2 to the side away from the trench 105-2), and between the shield connection trenches 105-1 and 105-2 in the y direction. the second section of the vertical trench 101 in the second region between (for example, the intermediate region 10M), and the side of the shield connection trench 105-2 (the side away from the side close to the shield connection trench 105-1 in the y direction) (e.g., the third section of trench 101 in the third region (eg, lower region 10L)). Source contact regions 103 on mesas 102 in all three regions may be contacted by source metal 720, for example.

A trench extending in the y direction above (for example, within upper region 10U), between (for example, within middle region 10M), and below (for example, within lower region 10L) horizontal shield connection trenches 105-1 and 105-2. 101 and mesa 102 and the corresponding sections of active trench 101 (and mesa 102) may be aligned with each other in the x direction (in other words, the first of trench 101 above horizontal shield connection trench 105-1 section, a second section of trench 101 between horizontal shield connection trenches 105-1 and 105-2, and a corresponding third section of trench 101 below horizontal shield connection trench 105-2, on a common y-axis (e.g., the axis Yt) and may not be offset relative to each other in the x direction). FIG. 6 shows, for example, trench section 101-U of trench 101 over horizontal shield connection trench 105-1, horizontal shield connection trenches 105-1 and 105, all aligned on a common y-axis (i.e., Yt). -2, and trench section 101-M of trench 101 below horizontal shield connection trench 105-2. Similarly, adjacent sections of mesa 102 above, between, and below horizontal shield connection trenches 105-1 and 105-2 are all aligned on a common y-axis (ie, Ym). In device 600, similar to device 200, horizontal shield connection trenches 105-1 are located above (e.g., trench section 10-U), between (e.g., trench section 10-M), and below (e.g., trench section 10-L). The corresponding sections of active trenches 101 (and mesas 102) extending in the y direction of and 105-2 are aligned with each other in the x direction and are not offset with respect to each other in the x direction.

In an exemplary implementation, both horizontal shield connection trenches 105-1 and 105-2 may be used as areas for contacting shield poly buried below the gate poly in the device. For example, an array 116A of insulator-covered conductive plugs 116 may be placed within trench 105-1 to create a shield poly contact, and an array 116B of insulator-covered conductive plugs 116 may be placed within trench 105-1. can be placed within trench 105-2. Having two horizontal shield connection trenches 105-1 and 105-2 increases the number of shield contacts that can be made compared to the number of shield contacts that can be made in a device using only a single shield connection trench. The number can be increased. In an exemplary implementation, source metal 720 may be used to connect to shield contacts formed in two horizontal shield connection trenches 105-1 and 105-2.

In an exemplary implementation, the device 600 includes a shield along the side or perimeter of the insulator-covered conductive plug 116, as described above with reference to device 200 (FIGS. 2A-2C). Gate poly deposited within connection trenches 105-1 and 105-2 may provide structural and electrical continuity of the gate electrode within trench 101 across shield connection trenches 105-1 and 105-2.

As previously discussed with reference to device 200, the buried shield poly layer in device 600 is a vertical insulator fabricated through the layer of gate poly 108 (FIG. 2A) in shield connection trenches 105-1 and 105-2. The contacts can be made by an array of conductive plugs 116 (116A and 116B) covered by the body. Each insulator-covered conductive plug 116 may be covered with an insulator (eg, oxide 110 in FIG. 2A) to form an inner opening 16. Inner opening 16 may be filled with a conductive material (eg, conductive material 109 of FIGS. 2A-2C) to contact shield poly buried beneath gate poly 108 within device 600. Gate poly 108 disposed along and around conductive plug 116 covered with vertical contact insulator was formed in active trench 101 across shield connection trenches 105-1 and 105-2 in device 600. Maintain electrical continuity of gate electrode.

As discussed above with reference to FIG. 6, device 600 includes a ) Corresponding sections of active trenches 101 (and mesas 102) extending in the y direction of horizontal shield connection trenches 105-1 and 105-2 are aligned with each other in the x direction and are offset with respect to each other in the x direction. do not have.

FIG. 7 shows an exemplary shield gate trench MOSFET device 700 having two shield connection trenches 105-1 and 105-2 that perpendicularly intersect active trench 101 and mesa 102, similar to device 600. However, in device 700, unlike device 600, the two shield connection trenches 105-1 and 105-2 are configured as termination trenches for a section of active trench 101. Furthermore, the section of active trench 101 (and mesa 102) that extends in the y direction between two horizontal shield connection trenches 105-1 and 105-2 (e.g., trench section 10-M) is configured to connect two horizontal shield connection trenches 105-1 and 105-2. Trenches 105-1 and 105-2 are offset in the x direction with respect to the upper and lower trench sections (eg, trench sections 10-U and 10-L). In FIG. 7, the offset distance between different trench sections is indicated as the distance DS in the x direction. In other words, the center section longitudinal trench (e.g., trench 101-M in trench section 10-M) is different from the first section and second section longitudinal trenches (e.g., trenches 101-U and 101-L). are parallel to the first and second lateral trenches (eg, horizontal shield connection trenches 105-1 and 105-2) and offset by a displacement distance DS. Staggering the active trench sections eliminates the need to handle large (4-way) trench intersections.

In an exemplary implementation, horizontal trenches (e.g., shield connection trenches 105 ) may include a plurality of short length, discontinuous trench segments, each traversing only a small number of trenches 101 and mesas 102 (eg, 2-5 trenches 101). Furthermore, these short length horizontal trench segments can traverse a small number of trenches 101 at different locations within the device layout.

FIG. 8 shows an exemplary shielded gate trench MOSFET device 800 in which short length horizontal trench segments intersect vertically with and across a small number of active trenches to create shielded poly contacts. Generate side areas for.

Device 800, like devices 600 and 700, may include an active trench 101 and a mesa 102 extending in the y direction between two gate feeds. The two gate feeds include two sheets or strips of gate metal (e.g., gate metal 710-1 and gate metal 710-2) connected to a gate electrode contact (e.g., contact 702) in the end region of active trench 101. formed by.

A first short length shield connection trench 105-3 traverses trenches 101-1, 101-2, and 101-c (as well as mesas 102-1 and 102-2) at approximately location Y1 on the y-axis. and extending laterally (eg, in the x direction). A second short length shield connection trench 105-4 extends across trenches 101-c, 101-3, and 101-4 (as well as mesas 102-3 and 102-4) at approximately location Y2 on the y-axis. (e.g., in the x direction).

As shown in FIG. 8, the short length shield connection trench 105-3 effectively divides each vertical trench 101-1 and 101-2 and each mesa 102-1 and 102-2 into two sections. (For example, an upper section of an upper region (e.g., region 12U) above shield connection trench 105-3 in the y direction, and a lower region (e.g., region 12U) below shield connection trench 105-3 in the y direction. 12L) lower section). A short length shield connection trench 105-4 effectively divides each vertical trench 101-3 and 101-4 and each mesa 102-3 and 102-4 into two sections (e.g., in the y direction, an upper section of an upper region (eg, region 14U) above shield connection trench 105-4; and a lower section of a lower region (eg, region 14L) below shield connection trench 105-4 in the y direction).

Due to their limited length or area, short length shield connection trenches 105-3 and 105-4 may be covered with a limited number of insulators to create shield poly contacts within device 800. Only the conductive plugs 116 that are connected can be accommodated. For example, arrays 116C and 116D, each comprising two insulator-covered conductive plugs 116, may be placed in short length shield connection trenches 105-3 and 105-4, respectively. However, there is a variety of locations where short length shield connection trenches 105-3 and 105-4 can be used (e.g. locations Y1 and Y2) and conductive plugs 116 covered with an insulator to create shield poly contacts. The resulting diversity in location provides flexibility in device design and robustness in processing.

In an exemplary implementation, a MOSFET device includes a set of vertical trenches and mesas that extend longitudinally across a semiconductor substrate from a gate feed. The device includes a first horizontal trench perpendicularly intersecting at least one of the set of vertical trenches and a vertical mesa at a first distance from the gate feed, the first horizontal trench perpendicularly intersecting at least one of the set of vertical trenches and the vertical mesa at a first distance from the gate feed; a second lateral trench in communication with the first lateral trench and perpendicularly intersecting at least one of the set of vertical trenches and vertical mesas in the semiconductor substrate at a second distance from the gate feed; , a second lateral trench in fluid communication with at least one of the set of intersecting longitudinal trenches.

In a MOSFET device, a shield poly layer is disposed within a set of vertical trenches and first and second horizontal trenches. An interpoly dielectric layer (IPD) and a gate poly layer are disposed over the shield poly layer within the set of vertical and horizontal trenches.

Additionally, in the MOSFET device, the first electrical contact to the shield poly layer includes a first insulator covered conductor that passes through the interpoly dielectric layer and the gate poly layer disposed within the first lateral trench. A second electrical contact to the shield poly layer is made by a conductive plug covered with a second insulator through an interpoly dielectric layer and a gate poly layer disposed within a second lateral trench. Produced by sex plug.

In a MOSFET device, a gate poly disposed in at least one of the set of vertical trenches intersected by a first horizontal trench includes a conductive plug covered with a first insulator passing within an interpoly dielectric layer. and forming a continuous gate electrode of the device uninterrupted by electrical contact to the shield poly layer made by the gate poly layer disposed within the first lateral trench. The gate poly disposed in at least one of the sets of vertical trenches intersected by the second lateral trench also includes a first insulator-covered conductive plug and a second insulator-covered conductive plug passing through the inter-poly dielectric layer. Forming a continuous gate electrode of the device uninterrupted by electrical contact to the shield poly layer made by the gate poly layer disposed within the lateral trenches.

In some example implementations of MOSFET devices, at least one of the set of vertical trenches intersected by the first lateral trench at a first distance is intersected by the second lateral trench at a second distance. one of a set of different vertical trenches.

In some exemplary implementations of MOSFET devices, at least one of the set of vertical trenches that the first lateral trench intersects at a first distance is such that the second lateral trench intersects at a second distance. one of a set of vertical trenches that are the same as the at least one vertical trench that intersects the at least one vertical trench;

In some exemplary implementations of MOSFET devices, at least one of the set of vertical trenches intersects a first lateral trench at a first distance and intersects a second lateral trench at a second distance. , a first section longitudinal trench on the side of the first transverse section, a central section longitudinal trench between the first and second transverse trenches, and a third section longitudinal trench on the side of the second transverse trench. be divided. In some exemplary implementations of the device, the intermediate section longitudinal trench is offset with respect to the first section and second section longitudinal trench by an offset distance parallel to the first and second transverse trenches. .

FIG. 9 illustrates an example method 900 for reducing shield electrode resistance in a shield gate trench MOSFET device.

Method 900 includes defining (910) a plurality of trenches of a first type in a semiconductor substrate. The plurality of trenches of the first type extend vertically (eg, from the gate feed region). The method 900 further includes intersecting (920) a trench of a second type extending laterally and intersecting the plurality of trenches of the first type, the trench of the second type intersecting the plurality of trenches of the first type. in fluid communication with each of the plurality of intersecting trenches of the type. The method 900 includes disposing (930) a shielding poly layer within the plurality of trenches of the first type and the trenches of the second type; disposing (940) an interpoly dielectric layer (IPL) and a gate poly layer over the shield poly layer and through openings in the interpoly dielectric layer and gate poly layer disposed in a second type of trench; forming (950) an electrical contact to the shield poly layer.

In the method 900, forming an electrical contact to the shield poly layer through the opening includes covering the opening with an insulator (e.g., an oxide) and a metal (e.g., tungsten), metal alloy, metal silicide, or placing one of the conductive polysilicon within the opening.

The method includes: defining a plurality of trenches of a first type in a semiconductor substrate, the plurality of trenches of a first type extending longitudinally; defining a second type of trench intersecting the first type of trench, the second type of trench intersecting with each of the first type of intersecting plurality of trenches; , disposing a shielding poly layer within the plurality of trenches of the first type and the trenches of the second type; and overlying the shielding poly layer within the plurality of trenches of the first type and the trenches of the second type. placing an interpoly dielectric layer (IPL) and a gate poly layer and providing electrical contact to the shield poly layer through openings in the interpoly dielectric layer and gate poly layer disposed within a second type of trench; and forming.

In the aforementioned method, forming electrical contact to the shield poly layer through the opening includes covering the opening with an insulator.

In the aforementioned method, forming an electrical contact to the shield poly layer through the opening includes disposing within the opening one of a metal, a metal alloy, a metal silicide, or a conductive polysilicon. .

In the aforementioned method, forming electrical contact to the shield poly layer through the opening includes placing tungsten within the opening.

The specific structural and functional details disclosed herein are merely representative for the purpose of describing example embodiments. However, the example embodiments may be embodied in many alternative forms and should not be construed as limited only to the embodiments set forth herein.

It will be understood that the particular number and geometric size and distribution of electrical contacts within the shield connection trenches are not limited to those shown in the drawings herein.

For example, the exemplary embodiments shown in the drawings herein have a specific number of electrical contacts (e.g., by conductive plugs 116 covered with an insulator) in the shield connection trench, and a geometric size. , and alignment. The exemplary embodiment illustrated in the drawings has, for example, one electrical contact in the shield connection trench per mesa or every two mesas, a width comparable to the width of one mesa or the width of two mesas. 1 illustrates electrical contacts and electrical contacts that are generally geometrically aligned, such as mesas; Other embodiments within the scope of this disclosure need not be limited to the representative examples shown in the figures herein. Other embodiments include, for example, aligned with the inter-mesa trench, or partially aligned with the mesa and inter-mesa trench, or randomly positioned within the shield connection trench without regard to alignment with the mesa or inter-mesa trench. may include electrical contacts. Other embodiments may include electrical contacts of any width that need not be an integer multiple or fraction of the mesa width (or inter-mesa trench width), for example. Similarly, other embodiments may include a number of contacts in the shield connection trench that is not an integer multiple or fraction of the number of mesas (or inter-mesa trenches), for example.

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations include, for example, various materials associated with semiconductor substrates, including, but not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and/or others. can be implemented using various types of semiconductor processing technology.

The terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the implementations. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. As used herein, the terms "comprises," "comprising," "includes," and/or "including" refer to the features described. , specifying the presence of a step, act, element, and/or component, but not excluding the presence or addition of one or more other features, steps, acts, elements, components, and/or groups thereof; will be better understood.

When an element, such as a layer, region, or substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it is referred to as being directly on, connecting to, electrically coupled to, or electrically coupled to another element. It will also be appreciated that there may be arrangable, connectable, or combinable or one or more intervening elements. On the other hand, when an element is referred to as being directly disposed on, directly connected to, or directly coupled to another element or layer, no intervening elements or layers are present. Throughout the detailed description of the present invention, elements illustrated as being directly, directly connected, or directly coupled may be may be referred to as such. The claims of this application may be amended to recite example relationships described or illustrated herein.

As used herein, the singular term may include the plural unless the context clearly dictates otherwise. Spatial relative terms (e.g., throughout, above, above, below, below, below, below, etc.) may be used to indicate different orientations of the device in use or operation in addition to that shown in the drawings. intended to be inclusive. In some implementations, the relative terms above and below can include vertically above and vertically below, respectively. In some implementations, the term adjacent can include laterally adjacent or horizontally adjacent.

Example implementations of the inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized implementations (and intermediate structures) of example implementations. Accordingly, variations from the shapes of the illustrative figures should be expected, for example as a result of manufacturing techniques and/or tolerances. Accordingly, example implementations of the inventive concepts should not be construed as limited to the particular shapes of regions illustrated herein, but should include deviations in shape resulting from, for example, manufacturing. be. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of the regions of the device and to limit the scope of the example implementations. nor is it intended to.

Terms such as "first", "second", etc. may be used to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Accordingly, a "first" element may be referred to as a "second" element without departing from the teachings of this implementation.

Unless otherwise defined, all terms (technical and scientific) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concepts pertain. Terms as defined in commonly used dictionaries are to be construed as having meanings consistent with their meaning in the relevant art and/or context of this specification, and are not expressly used herein. It will be further understood that the terms are not to be construed in an idealized or overly formal sense unless so defined.

While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will occur to those skilled in the art. Dew. It is therefore understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It is to be understood that these are presented by way of example only and not limitation, and that various changes in form and detail may be made. Any portions of the apparatus and/or methods described herein may be combined in any combination, except in mutually exclusive combinations. Implementations described herein may include various combinations and/or subcombinations of functionality, components, and/or features of different implementations described.

Claims (23)

A device (200, 300, 400, 500, 600, 700, 800),
A plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of a first direction type in a semiconductor substrate. A plurality of trenches of the first direction type (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101 -U) and
the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of a second direction type, the trenches (105, 105-1, 105-2, 105-3, 105-4) intersect with the plurality of trenches of the first direction type; (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U), and the longitudinal direction is in fluid communication with the transverse direction. a second direction type trench (105, 105-1, 105-2, 105-3, 105-4) perpendicular to the direction;
The plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first direction type and the second a shielding poly layer (111) disposed within said trenches (105, 105-1, 105-2, 105-3, 105-4) of a direction type;
the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U)) of the first direction type; an interpoly dielectric layer (IPL) ( 112) and a gate poly layer (108),
of the interpoly dielectric layer (112) and the gate poly layer (108) disposed within the trenches (105, 105-1, 105-2, 105-3, 105-4) of the second direction type; an electrical contact (116) to said shielding poly layer (111) disposed within an opening. the electrical contact to the interpoly dielectric layer (112) and the shield poly layer (111) disposed within openings (106, 16) of the gate poly layer (108) is covered with an insulator. The device according to claim 1, being a conductive plug (116). A conductive plug (116) covered with the insulator. 3. The device of claim 2, wherein is an oxide-covered conductive plug. 3. The conductive central portion (109) of the insulator-covered conductive plug (116) comprises one of a metal, a metal alloy, a metal silicide, or a conductive polysilicon. device. 3. The device of claim 2, wherein the electrically conductive central portion (109) of the insulator-covered electrically conductive plug (116) comprises tungsten. arranged in the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first direction type; the interpoly dielectric layer (112) disposed within the trenches (105, 105-1, 105-2, 105-3, 105-4) of the second directional type; ) and forming a continuous gate electrode of the device uninterrupted by the electrical contact to the shield poly layer disposed within the opening (106, 16) of the gate poly layer (108). The device according to item 1. A device (200, 300, 400, 500, 600, 700, 800),
A plurality of vertical trenches of a first direction type (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and vertical mesas (102, 102-1, 102-2, 102-3, 102-4),
The plurality of vertical trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, horizontal trenches (105, 105) of a second directional type extending in a transverse direction perpendicularly intersecting the longitudinal mesas (102, 102-1, 102-2, 102-3, 102-4); -1, 105-2, 105-3, 105-4), wherein the horizontal trench (105, 105-1, 105-2, 105-3, 105-4) is of the first direction type. fluid communication with the plurality of vertical trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U); (105, 105-1, 105-2, 105-3, 105-4) are each of the plurality of vertical trenches and vertical mesas (102, 102-1, 102-2, 102-3, 102-4). , the first section vertical trenches (101-U, 101-L, 101-M) on the first side of the horizontal trenches (105, 105-1, 105-2, 105-3, 105-4) and a first section mesa and a second section vertical trench on a second side opposite the first side of the horizontal trench (105, 105-1, 105-2, 105-3, 105-4); (101-U, 101-L, 101-M) and a second section vertical mesa, and the horizontal trenches (105, 105-1, 105-2, 105-3, 105-4) are divided into a lateral trench (105, 105-1, 105-2, 105-3, 105-4) in fluid communication with each of the first section longitudinal trench and the second section longitudinal trench;
The plurality of vertical trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the horizontal trenches (105, 105-1) , 105-2, 105-3, 105-4);
The plurality of vertical trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the horizontal trenches (105, 105-1) , 105-2, 105-3, 105-4) and an interpoly dielectric layer (IPL) (112) and a gate poly layer (108) disposed on the shield poly layer;
at least one layer extending through the interpoly dielectric layer (112) and the gate poly layer (108) disposed within the lateral trenches (105, 105-1, 105-2, 105-3, 105-4). an electrical contact to said shielding poly layer (111) by one insulator-covered conductive plug (116). The conductive plug (116) covered with the at least one insulator, the first section vertical mesa, and the second section vertical mesa are connected to the horizontal trench (105, 105-1, 105-2, 105-3). , 105-4) aligned along a common axis perpendicular to . The conductive plug (116) covered with the at least one insulator, the first section vertical mesa, and the second section vertical trench are connected to the horizontal trench (105, 105-1, 105-2, 105-3). , 105-4). 105-4). The plurality of vertical trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and vertical mesas (102, 102-1, 102-2, 102-3, 102-4) each has a trench width and a mesa width, and the conductive plug (116) covered with the at least one insulator is equal to the mesa width; 8. The device of claim 7, wherein the device has a width of or less than that. The plurality of vertical trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and mesas (102, 102-1, 102 -2, 102-3, 102-4) have a trench width and a mesa width, and the conductive plug (116) covered with the at least one insulator has a width greater than the mesa width. 8. The device of claim 7. 12. The device of claim 11, wherein the at least one insulator-covered conductive plug (116) has a width approximately equal to the sum of two mesa widths and a trench width. the at least one insulator-covered conductive plug (116) includes a number of insulator-covered conductive plugs disposed within the lateral trench; The number of plugs is determined by the number of vertical trenches in the plurality of vertical trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U). 8. The device of claim 7, wherein the number of devices is approximately the same. The at least one insulator covered conductive plug (116) comprises a number of insulators disposed within the lateral trenches (105, 105-1, 105-2, 105-3, 105-4). The number of conductive plugs covered with the insulator is the same as that of the plurality of vertical trenches (101, 101-1, 101-2, 102-3, 10-4, 101- 8. The device of claim 7, wherein the number of vertical trenches in (c, 101-L, 101-M, 101-U) is approximately half. the at least one insulation within the interpoly dielectric layer (112) and the gate poly layer (108) disposed within the lateral trenches (105, 105-1, 105-2, 105-3, 105-4); 8. A device according to claim 7, wherein a body-covered electrically conductive plug (116) is arranged in the space between the first section mesa and the second section mesa. The at least one insulator covered conductive plug in the interpoly dielectric layer (112) and the gate poly layer (108) is an oxide covered opening (106, 16). The device according to item 7. The electrical contact to the shielding poly layer (111) through the at least one insulator-covered conductive plug (116) is one of metal, metal alloy, metal silicide, or conductive polysilicon. 8. The device of claim 7, comprising: 8. The device of claim 7, wherein the electrical contact to the shielding poly layer (111) through the at least one insulator covered conductive plug (116) comprises tungsten. The plurality of vertical trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the horizontal trenches (105, 105-1) , 105-2, 105-3, 105-4), the inter-poly dielectric layer (112) located within the lateral trench and the gate poly layer (108) forming a continuous gate electrode of the device uninterrupted by the electrical contact to the shielding poly layer (111) by a conductive plug (116) covered with the at least one insulator through the conductive plug (116). The device according to item 7. A method,
a plurality of trenches of the first type (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) in the semiconductor substrate; , a plurality of trenches of the first type (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101 -U); and
The plurality of trenches of the first type (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101- a second type of trench (105, 105-1, 105-2, 105-3, 105-4) that intersects with the plurality of intersecting trenches (101, 101) of the first type; -1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U). -1, 105-2, 105-3, 105-4);
the plurality of trenches of the first type (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the second type; arranging a shielding poly layer (111) within said trenches (105, 105-1, 105-2, 105-3, 105-4) of type;
the plurality of trenches of the first type (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the second type; An interpoly dielectric layer (IPD) (112) and a gate poly layer ( 108) and
openings in the interpoly dielectric layer (112) and the gate poly layer (108) disposed within the trenches (105, 105-1, 105-2, 105-3, 105-4) of the second type; forming an electrical contact to the shield poly layer (111) through the portion (106, 16). 21. Forming the electrical contact to the shielding poly layer (111) through the opening (106, 16) comprises covering the opening (106, 16) with an insulator. the method of. Forming the electrical contact to the shielding poly layer (111) through the opening (106, 16) comprises depositing in the opening one of metal, metal alloy, metal silicide, or conductive polysilicon. 21. The method of claim 20, comprising placing one. 21. The method of claim 20, wherein forming the electrical contact to the shield poly layer (111) through the opening (106, 16) comprises placing tungsten within the opening.

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