TW202249294A - Shield contact layout for power mosfets - Google Patents

Abstract

A method includes defining a plurality of trenches of a first type that extend in a longitudinal direction in a semiconductor substrate, and defining a trench of a second type extending in a lateral direction and intersecting the plurality of trenches of the first type. The trench of the second type is in fluid communication with each of the intersected plurality of trenches of the first type. The method further includes disposing a shield poly layer in the plurality of trenches of the first type and the trench of the second type, disposing an inter-poly dielectric layer and a gate poly layer above the shield poly layer in the plurality of trenches of the first type and the trench of the second type, and forming an electrical contact to the shield poly layer through an opening in the inter-poly dielectric layer and the gate poly layer disposed in the trench of the second type.

Description

Shield contact layout for power MOSFETs

This note is about contacts in shielded gate trench MOSFETs.

Buried polysilicon shield electrodes are used in shielded gate trench MOSFETs for charge balancing and to reduce the drain-source on-resistance (RDS _on ) of the device. However, the resistance and stray capacitance associated with the polysilicon shield electrode can affect the device, for example, by causing undesired gate bounce or low avalanche capability during unclamped inductive switching (UIS) in the device circuit. electrical performance, or otherwise affect application efficiency. As semiconductor devices (e.g., device cell size) and lithography design rules shrink, it becomes increasingly difficult to fabricate low-resistance buried polysilicon shield electrodes in semiconductor devices (e.g., shielded gate trench MOSFETs) to avoid or reduce e.g. Extreme jump and poor avalanche capability.

In a general aspect, a device includes a plurality of trenches of a first orientation type extending in a longitudinal direction in a semiconductor substrate; and a trench of a second orientation type extending in a lateral direction A direction extends and intersects the plurality of grooves of the first direction type. The longitudinal direction is orthogonal to the transverse direction. The groove of the second directional type is in fluid communication with each of the plurality of intersecting grooves of the first directional type.

The device further includes a shielding polysilicon layer disposed in the plurality of trenches of the first orientation type and the trenches of the second orientation type; an inter-poly dielectric layer (IPL) ) and a gate polysilicon layer disposed over the shielding polysilicon layer in the plurality of trenches of the first directional type and the trenches of the second directional type; and an electrical connection to the shielding polysilicon layer Contacts disposed within an opening in the interpoly dielectric layer and the gate polysilicon layer disposed in the trench of the second orientation type.

In a general aspect, a device includes a plurality of longitudinal trenches and longitudinal mesas of a first orientation type extending parallel in a longitudinal direction across a semiconductor substrate; and a lateral orientation of a second orientation type. A trench extending in a transverse direction perpendicular to the longitudinal direction and perpendicularly intersects the plurality of longitudinal trenches and longitudinal mesas of the first direction type. The lateral groove is in fluid communication with the plurality of longitudinal grooves of the first directional type. The lateral groove divides each of the plurality of longitudinal grooves and longitudinal mesas into a first segmental longitudinal groove and a first segmental mesa on a first side of the lateral groove, and relative to a second segment longitudinal groove and a second segment longitudinal mesa on a second side of the first side of the lateral groove, the longitudinal groove and the plurality of first segment longitudinal grooves and Each of the second section longitudinal grooves is in fluid communication.

The device further includes a shielding polysilicon layer disposed in the plurality of longitudinal trenches and the lateral trenches; an interpolysilicon dielectric layer (IPL) and a gate polysilicon layer disposed in the plurality of longitudinal trenches a trench and the lateral trench disposed above the shielding polysilicon layer; and an electrical contact to the shielding polysilicon layer via at least one insulator lined conductive plug extending through the lateral trench disposed above the shielding polysilicon layer The interpolysilicon dielectric layer and the gate polysilicon layer in the trench.

In a general aspect, a method includes defining a plurality of trenches of a first type in a semiconductor substrate. The plurality of grooves of the first type extend in a longitudinal direction. The method further includes defining a trench of a second type extending in a lateral direction and intersecting the plurality of trenches of the first type. The groove of the second type is in fluid communication with each of the plurality of grooves of the first type that intersect. The method further includes disposing a shielding polysilicon layer in the plurality of trenches of the first type and the trenches of the second type; disposing an interpolysilicon dielectric (IPD) and a gate polysilicon layer in trenches above the shielding polysilicon layer; and forming an electrical contact to the shielding polysilicon layer through the An opening in the interpolysilicon dielectric layer and the gate polysilicon layer in the trench.

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices are used in many power switching applications. In a typical MOSFET device, the gate electrode provides on and off control of the device in response to an applied gate voltage. For example, in an N-type enhancement MOSFET, turn-on occurs when a conductive N-type inversion layer (ie, the channel region) forms in the p-type body region in response to a positive gate voltage exceeding an intrinsic threshold voltage. The inversion layer connects the N-type source region to the N-type drain region and allows majority carrier conduction between these regions.

In a trench MOSFET device, the gate electrode is formed in a trench extending downward (eg, vertically downward) from a major surface of a semiconductor material (also referred to as a semiconductor region), such as silicon. Further, a shield electrode may be formed in the trench below the gate electrode (and insulated by an inter-electrode or inter-poly dielectric). Current flow in trench MOSFET devices is predominantly vertical (eg, in the N-doped drift region), and thus, device cells can be more densely packed. For example, a device cell may include a trench containing a gate electrode and a shield electrode, and adjacent mesas containing the drain, source, body, and channel regions of the device.

The current handling capability of a Trench MOSFET device is determined by its gate channel width. To minimize cost, keep the die area size of the transistor as small as possible and increase the width of the channel surface area (i.e., increase the "channel density") by creating a honeycomb structure that repeats over the entire area of the MOSFET die Can be important. The way to increase channel density (and thus increase channel width) is to reduce the size of the device units and pack more device units at a smaller pitch in a given surface area.

Example trench MOSFET devices may include an array of hundreds or thousands of device cells, each including a trench and an adjacent mesa. A device unit may be referred to herein as a trench-mesa unit, since each device unit geometrically includes a trench structure and a mesa (or two half-mesa) structure. Shield electrodes and gate electrodes may be formed inside linear trenches (eg, trench 101 ) running (eg, aligned along the mesas) along the mesas (eg, mesas 102 ). The shield and gate electrodes can be made of polysilicon (eg, "n+ shield poly" and "n+ gate poly") and separated from each other by a dielectric layer (eg, interpolysilicon dielectric (IPD) layer 112 of FIG. 2B ) . The IPD layer can be, for example, an oxide layer. The shield and gate electrodes are also isolated from the silicon in the mesas by dielectric layers (eg, shield and gate dielectric layers).

To ensure proper electrical contact of each cell, a "planar stripe" structure is often used to fabricate trench MOSFETs on the surface of a semiconductor die. In a planar strip structure, the gate electrode ("gate") and shield electrode ("shield poly") within a trench (eg, a linear trench) are arranged in longitudinal strips (eg, along the length of the trench) along the length of the trench. aligned with the length of the groove). A trench that includes a gate electrode and a shield electrode may be referred to as an active trench. The gate electrode (eg, made of gate polysilicon) is disposed along the length of the active trench over the shield electrode (eg, made of shield polysilicon). ) on (or above) the top of the . The gate polysilicon in the active trenches is exposed and contacted by the gate runner (eg, gate metal) at the ends of the stripes, and the shield electrode (shield polysilicon) in the trenches can be exposed and contacted along the active The location of the trench length is raised to the surface (using a masking step) for contact by the source metal.

In modern trench MOSFET devices (eg, with narrow linewidths), shield resistance is a factor that affects device efficiency and performance. Lower shield resistance can be achieved by creating multiple contacts to the shield poly in the active trench (for example, by raising the shield poly vertically to the surface at multiple locations to create multiple shield contacts to the source metal pieces) obtained.

Lifting the shield polysilicon (from directly below the gate polysilicon) vertically to the surface interrupts or destroys the continuity of the gate polysilicon running along the length of the active trench. The gate polysilicon is broken into two discrete segments along the active trench length by instances of shield polysilicon raised vertically to the surface. In an example embodiment, two separate gate runners or gate metal strips at the ends of the strip (eg, gate metal 710-1, 710-2 as shown in, for example, FIGS. 6 and 7 ) Contact may be required to two discrete gate polysilicon segments created by a single instance of shielding polysilicon vertically lifted through the active trench to the surface. Many instances of lifting the shield poly vertically through the gate poly to the surface along the length of the active trench results in several separate gate poly segments that are floating (i.e., not separated by two separate gate polysilicon segments). runner contact), and thus multiple gate runners are required to contact each gate polysilicon segment, which occupies die area.

The present disclosure herein describes example device configurations or layouts for making contacts to shield electrodes buried under gate electrodes in active trenches of MOSFET devices fabricated in semiconductor substrates. Make contacts (eg, metal, metal alloy, metal silicide, conductive polysilicon, or other conductive material contacts) to shield polysilicon buried in shield connection trenches perpendicular to and transverse to the active trenches below the gate polysilicon. The shield connection trench may be tied to the trench portion on the active trench side. Contacts are made through vertical insulator-lined (eg, oxide-lined) openings extending from the top surface through the gate poly overlying the shield electrode to the buried shield poly. The buried shield polysilicon stays in place under the gate polysilicon and is not raised to the surface. Instead, contacts to the shield polysilicon are made by depositing a conductive material (eg, tungsten metal) in the openings. The gate polysilicon is wound in the horizontal plane around the opening in the shield connection trench to preserve a portion of the gate electrode's active trench on one side of the contact and the active trench on the opposite side of the contact. Continuity in the corresponding part.

1 shows a portion of an example device mask layout 100 for a shielded gate trench MOSFET device (e.g., device 200 of FIGS. 2A, 2B, and 2C) in which multiple contacts to the shield electrode can be made. . Figure 1 shows, for example, a device mask layout 100 in the x-y plane (the x-y plane may be aligned along the plane of a silicon wafer or semiconductor substrate of a transistor device).

For ease of description, the relative orientations or coordinates of features of the disclosed trench MOSFET devices (e.g., trenches 101 and 105, mesas 102, etc.) may be referred to herein with reference to, for example, the x-axis and y-axis shown on the page of FIG. describe. A direction perpendicular to the x-y plane of the page (eg, the z-axis) may be referred to as a vertical direction or axis. The z-direction can be the direction down into the depth of the semiconductor substrate, and can be aligned in the direction of, for example, the depth of trenches in MOSFET devices fabricated in the semiconductor substrate. Furthermore, for visual clarity, a limited number of trenches/device units (eg, 3 to 5 trenches/device units) of the array of trenches/device units in device mask layout 100 are shown in FIG. 1 . As previously mentioned, a practical MOSFET device may include an array of hundreds or thousands of trenches/device cells, which may be achieved, for example, by repeating (e.g., in the x-direction) that shown in the example device mask layout 100. A finite array structure is obtained.

The device mask layout 100 shown in FIG. 1 includes several active trenches (ie, longitudinal trenches 101 ) of the device that are (eg, in the y-direction) parallel (eg, substantially parallel) to each other along Row. A mesa 102 may be formed between the pair of longitudinal grooves 101 . The trench 101 and the mesa 102 may be a linear trench and a linear mesa (for example, running in the y direction), respectively. Trenches 101 and mesas 102 may have uniform widths Wt and Wm, respectively (eg, horizontal widths in the x-direction). Device elements such as source and body regions (not shown) may be formed in the mesas 102 and contacted at source contact regions 103 , for example by source metal (not shown). Device elements (eg, source and body regions) may be formed, for example, by n-type source and drain (NSD) implants in section 104 of device mask layout 100 .

Although only a small number of trenches 101 and mesas 102 (e.g., four trenches and three mesas) are shown in FIG. 1 (and other figures herein), it should be noted that actual MOSFET devices may include hundreds or thousands of An array of trenches/device units can be obtained, for example, by repeating (eg in the x-direction) the trench and mesa structures or patterns shown in the drawings.

A horizontal or lateral trench (eg, shield connection trench 105 ) (side trench) may extend laterally (eg, in the x direction) to intercept and traverse at a distance Y along the y-axis (ie, truncated) trench 101 and mesa 102. The shield connection trench 105 may, for example, have a vertical width Wv in the y-direction. The shield connection trench 105 can effectively divide each longitudinal trench 101 and each mesa 102 into two sections (for example, wherein the upper section of the longitudinal trench 101 is in the shield connection trench 105 in the y direction of the device mask layout 100 In the upper region above (for example, region 10U), and the lower section of the trench 101 is in the lower region of the device mask layout 100 below the shield connection trench 105 in the y-direction). The trenches (ie, trench 101 and trench 105 ) may have approximately the same depth (not shown) (eg, with reference to the top surface of mesa 102 ).

In an example embodiment, two sections of the longitudinal trench 101 (ie, the upper region of the longitudinal trench 101 in the upper region 10U) on either side (ie, above and below) of the shield connection trench 105 segment and the lower section of the longitudinal groove 101 in the lower region 10L) may be aligned in the horizontal x-direction (i.e., shared or on the common y-axis Yt).

The shield connection trench 105 may be in fluid communication with each of the divided sections of the trench 101 (in other words, the shield connection trench 105 has a physical opening to each of the divided sections of the trench 101 such that fluid (i.e., no A gas or liquid of fixed shape) can easily flow from the shield connection trench 105 through the opening into each of the divided sections of the trench 101 , or vice versa). Shield and gate electrodes (not shown) of the device may be formed in trench 101 , for example, by depositing shield polysilicon and gate polysilicon in trenches 101 and 105 . The shield polysilicon and gate polysilicon may be separated by an interpolysilicon dielectric (IPD) layer (not shown in FIG. 1 ).

Shield polysilicon in shield connection trench 105 may be exposed (for making contacts in trenches 101 and 105 to the shield electrode through one or more openings (e.g., opening 106) from the gate The top surface of the pole poly is made through the gate poly and IPD layer in the shield connection trench 105 to reach the underlying shield poly. In an example embodiment, an insulator lined conductive plug (eg, as shown at least in FIGS. 2A, 2B , and insulator-lined conductive plug 116 in FIG. 2C) may be fabricated in opening 106. Insulator-lined conductive plug 116 may, for example, include a conductive central portion made of conductive material 109 (FIG. 2A) formed by concentric insulating The outer part (made of oxide 110 (FIG. 2A) surrounds.

In an example implementation, referring back to device mask layout 100 (FIG. 1), opening 106 may first be filled with an oxide (eg, oxide 110 of FIG. 2A) or other insulator, and thereafter, another opening may be made through An oxide or other insulator is filled to form an insulator-lined opening (eg, opening 16 ) to again reach the underlying shield polysilicon. In the device mask layout 100 shown in FIG. 1 , this other insulator-lined opening (ie, opening 16 ) is shown as a rectangle in dashed-line format inside opening 106 .

Metal or other conductive material (eg, conductive material 109 of FIG. 2A ) may be deposited in the oxide-lined opening 16 to establish electrical contact with the underlying shield polysilicon for use with, for example, the source metal of the device (eg, 6 to 9 source metal 720) connection.

In an example embodiment, the gate polysilicon deposited in the shield connection trench 105 along one side or around the insulator lined conductive plug 116 formed in the opening 106 may be in the trench 101 across the shield connection trench 105 Structural and electrical continuity of the gate electrode is provided (in other words, the gate polysilicon in the segment of the trench 101 in the upper region 10U is continuous with the gate polysilicon in the corresponding segment of the trench 101 in the lower region 10U).

In an example implementation, openings 106 and 16 (and insulator-lined conductive plug(s) 116 ) may have a square shape, a rectangular shape, a circular shape, an oval shape, or any other shape in the x-y plane. In an example implementation as shown in FIG. 1 , the opening 106 may have a rectangular shape, eg, having a width Wo in the x-direction and a length Lo in the y-direction. In example embodiments, the width Wo may be greater than, the same as, or less than the width Wm of the mesas 102 .

In an example embodiment, for a MOSFET having a breakdown voltage BVDSS of 25V to 30V, the trench 101 may have a width Wt, for example, in the range of about 0.2µm to 1.0µm (eg, 0.3µm); the mesa 102 may have a width, for example, between Width Wm in the range of approximately 0.2 µm to 1.0 µm (eg, 0.3 µm); shield contact trench 105 may have a width Wv, eg, in the range of approximately 0.5 µm to 2.0 µm (eg, 1.0 µm); insulator lined The conductive plug 116 may have a width Wo in the range of about 0.3 µm to 2.0 µm (eg, 1.4 µm) and a length Lo in the range of about 0.3 µm to 1.2 µm (eg, 0.6 µm); and the contact opening 16 There may be an x-direction width in the range of about 0.1-1.8 µm (eg, 1.0 µm) and a y-direction length of about 0.1-1.0 µm (eg, 0.2 µm).

For MOSFETs with a breakdown voltage BVDSS higher than 30V, the dimensions of the aforementioned features (e.g., width Wt of trench 101, width Wm of mesa 102, width Wv of shield contact trench 105, width of insulator-lined conductive plug 116 Wo and length Lo, and width and length of contact opening 16 ) may be greater than the example values given above for a MOSFET with a breakdown voltage BVDSS of 25V to 30V.

In an example embodiment, an array of several openings 106 (eg, array 106A) may be disposed along the x-axis in shield connection trench 105 to form a corresponding array (116A) of insulator-lined conductive plug(s) 116 ) (Fig. 2A).

In the example implementation shown in FIG. 2A , the insulator-lined conductive plugs 116 in the shield connection trenches 105 may be aligned in the y-direction with the mesas 102 of the upper region 10U and corresponding mesas 102 of the lower region 10L (in other words , each insulator-lined conductive plug 116 , the mesa 102 of the upper region 10U, and the corresponding mesa 102 of the lower region 10L may all lie along a common axis (eg, axis Ym of FIG. 2A ) in the y-direction).

2A shows an example shielded gate trench MOSFET device 200 having gate electrodes that are continuous around and not bounded by shield contacts fabricated to the shield polysilicon below the gate electrodes. Interruption (that is, no interruption). In an example implementation, device 200 may be fabricated using, for example, device mask layout 100 . In the example shown in FIG. 2A , device 200 includes active trenches 101 and mesas 102 running in the y-direction and horizontal shield connection trenches extending laterally (e.g., in the x-direction) across trenches 101 and mesas 102. Groove 105 (side groove). Corresponding sections of the active trenches 101 (and mesas 102 ) extending in the y-direction above and below the horizontal shield connection trenches 105 may be aligned with each other in the x-direction (in other words, the sections of the trenches 101 above Segments of corresponding trenches 101 below and below may share a common y-axis (eg, axis Yt) and are not staggered relative to each other in the x-direction). 2A shows, for example, a segment 101-U of a trench 101 above a horizontal shield connection trench 105 and a segment 101-L of a corresponding trench 101 below, which are aligned on a common y-axis (ie, Yt). . Similarly, adjacent segments of mesas 102 above and below horizontal shield connection trenches 105 are aligned on a common y-axis (ie, Ym).

In an example embodiment, the gate polysilicon deposited in the shield connection trench 105 along one side or around the insulator-lined conductive plug 116 can provide the structure of the gate electrode in the trench 101 across the shield connection trench 105 and electrical continuity (in other words, throughout the shield connection trench 105, the gate polysilicon in the segment of the trench 101 in the upper region 10U and the gate polysilicon in the corresponding segment of the trench 101 in the lower region 10U continuous).

Gate oxide 107 may be grown or deposited on the sidewalls of mesa 102 bordering active trench 101 and shield connection trench 105 . A gate polysilicon layer 108 may be deposited in the active trench 101 and the shield connection trench 105 to overshadow the shield polysilicon layer (shield polysilicon layer 111 of FIG. 2B ) and interpolysilicon dielectric (IPD) layer 112 previously deposited in the trenches. (IPD layer 112 of FIG. 2B ) is formed over the gate electrode. The shield polysilicon layer and the IPD layer are not visible in FIG. 2A because they are buried under the gate polysilicon 108 .

In device 200 , the buried shield polysilicon layer is contacted by an array (eg, array 116A) of vertical insulator-lined conductive plugs 116 formed in shield connection trench 105 through gate polysilicon layer 108 and IPD 112 . Each insulator-lined conductive plug 116 may include a conductive central portion surrounded by an insulating liner. In an example embodiment, the insulating liner can be made of an insulating material, such as oxide 110 , and the conductive center portion can be made of a conductive material 109 , such as tungsten. The conductive material 109 (eg, tungsten) of each insulator-lined conductive plug may electrically contact the gate polysilicon 108 buried in the device 200 and the shield polysilicon beneath the IPD layer 112 . The gate polysilicon 108 along and around the vertical insulator lined conductive plug 116 can maintain electrical continuity of the gate electrode formed in the active trench 101 across the shield connection trench 105 .

The electrical contact to the buried shield poly layer is made by at least one insulator lined conductive plug 116 passing through the interpoly dielectric layer 112 and the gate poly layer 108 disposed in the shield connection trench 105 To reach the buried shield polysilicon layer.

In an example implementation, the number of vertical insulator-lined conductive plugs 116 in shield connection trenches 105 may be equal to (or approximately equal to) the number of active trenches 101 (or mesas 102 ) intersecting shield connection trenches 105 . Further, in the example embodiment shown in FIG. 2A , each insulator-lined conductive plug 116 may be disposed between a section of the mesa 102 in the upper region 10A and a corresponding section of the mesa 102 in the lower region 10L. in the space between. Each insulator-lined conductive plug 116 may have a rectangular shape with a width Wo in the x-direction and a length Lo in the y-direction. In an example implementation, as previously mentioned, the width Wo may be greater than, the same as, or less than the width Wm of the mesa 102 . In an example implementation such as that shown in FIG. 2A, width Wo may be about two to three times as large as length Lo.

2B and 2C show cross-sectional views of portions of device 200 . 2B shows a portion spanning, for example, a segment of mesa 102 in upper region 10A and a corresponding segment of mesa 102 in lower region 10L, shield connection trench 105, and insulator-lined conductive plug 116 (disposed on Cross-sectional view (taken in the z-y plane along line A-A of FIG. 2A ) between mesas 102. Insulator-lined conductive plug 116 includes a conductive central portion (eg, conductive material 109 ) consisting of a concentric insulating outer portion (eg, oxide 110). Figure 2B shows an insulator-lined conductive plug 116 passing through the gate polysilicon 108 and the IPD 112 to reach the buried shield polysilicon layer 111 in the shield connection trench 105. The insulator-lined conductive plug 116 The conductive material 109 (for example, tungsten) of the conductive central portion of the conductive core electrically contacts the buried shield polysilicon layer 111 in the shield connection trench 105. The buried shield polysilicon layer 111 can be connected by a dielectric layer (for example, an oxide layer 113 ) to isolate the bottom and sides of the shield connection trench 105 .

FIG. 2C shows a cross-sectional view (taken in the z-x plane along line B-B of FIG. 2A ) across, for example, along a portion of the shield connection trench 105 and the two insulator-lined conductive plugs 116 . FIG. 2C shows, for example, two insulator lined conductive plugs 116 passing through gate polysilicon 108 and IPD 112 to reach buried shield polysilicon layer 111 in shield connection trench 105 . As in FIG. 2B , each of the two insulator-lined conductive plugs 116 includes a conductive central portion (eg, conductive material 109 ) surrounded by a concentric insulating outer portion (eg, oxide 110 ). The conductive material 109 (eg, tungsten) electrically contacts the buried shield polysilicon layer 111 in the shield connection trench 105 .

As previously mentioned, in the example implementation shown in FIG. 2A , the corresponding segments of active trenches 101 (and mesas 102 ) extending in the y-direction above and below the horizontal shield connection trenches 105 are in the x-direction. are aligned with each other and are not staggered relative to each other in the x-direction). The intersection of the shield connection trenches 105 with the longitudinal trenches 101 having non-staggered segments can create a four-way (x-y) intersection of the trenches, as depicted by arrow 11 of FIG. 2A .

FIG. 3 shows another example shielded gate trench MOSFET device 300 having gate electrodes that are continuous around shield contacts fabricated to the shield polysilicon below the gate electrodes in the horizontal shield connection trenches. are not interrupted by the shield contacts (eg, no interruptions). In device 300, corresponding sections of active trenches 101 (and mesas 102) extending in y-direction above and below horizontal shield connection trenches 105 are relative to each other in x-direction, for example by a distance DS in x-direction staggered. Shield connection trenches 105 may serve as termination trenches for alternating sections of longitudinal trenches 101 and may create a three-way (x-x-y) intersection of trenches, as depicted by arrow 12 of FIG. 3 . Under some processing conditions, the three-way intersection of the treatment grooves may be superior to the four-way intersection of the treatment grooves (arrow 11 of Fig. 2A),

4 and 5 show other example shielded gate trench MOSFET devices (i.e., device 400 and device 500, respectively) having gate electrodes fabricated into horizontal shield connection trenches. The shield contacts of the shield polysilicon under the gate electrodes are continuous around and not interrupted by the shield contacts. In device 400 and device 500, as in device 200, corresponding sections of active trenches 101 (and mesas 102) extending in the y-direction above and below the horizontal shield connection trenches 105 face each other in the x-direction aligned and not staggered relative to each other in the x-direction. However, the number of vertical insulator-lined conductive plugs 106 in shield connection trenches 105 may be less than the number of active trenches 101 (or mesas 102 ) intersecting shield connection trenches 105 .

In an example implementation, the number of vertical insulator-lined conductive plugs 106 in shield connection trenches 105 may be equal to about half the number of active trenches 101 (or mesas 102 ) intersecting shield connection trenches 105 .

In one example implementation (device 400) shown in FIG. 4, each insulator-lined conductive plug 106 can have a width Wo (in the x-direction) that is greater than Wm of the mesa 102 (e.g., Wo can be about two times Wm). doubled). In an example implementation, Wo may be approximately equal to or greater than the sum of the width (Wm) of the mesa 102 and the width (Wt) of the trench 101 . Further, in the example embodiment shown in FIG. 4 , each insulator-lined conductive plug 106 in the shield connection trench 105 may be disposed between a section of a pair of mesas 102 in the upper region 10U and the lower region In the space between a pair of corresponding sections of the pair of mesas 102 in 10L. Each insulator-lined conductive plug 106 may have a rectangular shape with a width Wo in the x-direction and a length Lo in the y-direction. In an example implementation, as previously mentioned, the width Wo may be greater than the width Wm of the mesas 102 . For example, in the example embodiment shown in FIG. 4, the width Wo may be approximately equal to the width of two mesas (2Wm) and the width of a trench (Wt), ie, Wo may be approximately equal to 2*Wm+Wt.

FIG. 5 shows another example implementation of a device having a number of vertical insulator-lined conductive plugs 106 equal to about half the number of active trenches 101 in shield connection trenches 105 . In device 500 , each insulator-lined conductive plug 106 may have a width Wo (in the x-direction) that is less than width Wm of mesa 102 . Further, in the example embodiment shown in FIG. 5 , each insulator-lined conductive plug 106 in the shield connection trench 105 may be disposed in a segment of alternating mesas 102 between the upper region 10A and the lower region 10L. In the space between the corresponding sections of the alternating mesas 102 . In other words, with respect to the first mesa 102, the open insulator lined conductive plug in the shield connection trench 105 may be disposed between the section of the first mesa 102 in the upper region 10U and the first mesa 102 in the lower region 10L. However, with respect to the second (adjacent) mesa 102 , an insulator-lined conductive plug 106 is disposed between the upper and lower sections of the second mesa 102 .

In the example shown in FIGS. 1-5 , the longitudinal active trenches and mesas (eg, trench 101 and mesa 102 ) extend longitudinally (eg, along the y-axis or y-direction) from the gate contact area (gate feed). Vertical active trenches and mesas may, for example, extend between two gate feeds (eg, gate metal 710-1 and gate metal 710-2 of FIGS. 6-8). The plurality of longitudinal active trenches and mesas may, for example, be vertically traversed by a single horizontal shield connection trench 105 and a single linear array (e.g., array 106A) of insulator-lined conductive plugs disposed in shield connection trench 105, which The array is used to make shield contacts to the shield polysilicon in the device.

Figures 6, 7, 8, and 9 show other example implementations in which a vertical active trench between two gate feeds (eg, gate metals 710-1 and 710-2 of Figures 6-8) and mesas (e.g., trenches 101 and mesas 102) are vertically traversed by a linear array (e.g., array 106A) of more than one horizontal shield connection trenches and more than one insulator-lined conductive plugs, which can be used in Shield contacts are fabricated in the device to the shield polysilicon in the horizontal shield connection trenches.

FIG. 6 shows another example shielded gate trench MOSFET device 600 having gate electrodes that are continuous around and not contacted by shield contacts fabricated to the shield polysilicon below the gate electrodes. The file is interrupted. In the example shown in FIG. 6 , device 600 includes active trenches 101 and mesas 102 of a first direction type extending parallel in a longitudinal direction (eg, along the y-direction) between two gate feeds. The two gate feeds are formed from two sheets or strips of gate metal (e.g., gate metal 710-1 and gate metal 710-2), which are connected to the gate in the end region of the active trench 101. Pole electrode contacts (eg, contacts 702 ).

The first horizontal shield connection trench 105-1 (side trench) of the second direction type extends laterally in a lateral direction (for example, along the x-direction) and is connected to the trench 101 and the trench 101 at an approximate position Y1 on the y-axis. The mesas 102 intersect. The second horizontal shield connection trench 105 - 1 (side trench) of the second direction type extends laterally in a transverse direction (for example, along the x direction) that is orthogonal to the longitudinal direction, and is approximately at a position Y2 on the y axis. intersects the trench 101 and the mesa 102 . The shield connection trenches 105-1 and 105-2 can effectively divide each longitudinal groove 101 and each mesa 102 into three sections (for example, wherein the first section of the longitudinal trench 101 is in the shield connection trench 105-1 In the first region (for example, the upper region 10U) on one side (away from the side closer to the shield connection trench 105-2 in the y direction), the second section of the longitudinal trench 101 is interposed in the y direction. In the second area between the shield connection trenches 105-1 and 105-2, and the third section of the trench 101 is on one side of the shield connection trench 105-2 (farther away from the shield connection in the y direction) One side of the trench 105 - 1 ) in the third region (eg, the lower region 10L)). The source contact regions 103 on the mesas 102 in all three regions may be contacted, for example, by source metal 720 .

Above (for example, in the upper region 10U), between (for example, in the middle region 10M), and below (for example, in the lower region 10L) the horizontal shield connection trenches 105-1 and 105-2 in the y direction Sections of trenches 101 and mesas 102 extending above and corresponding sections of active trenches 101 (and mesas 102 ) may be aligned with each other in the x-direction (in other words, trenches 101 above horizontal shield connection trenches 105-1 the first section of the trench 101 between the horizontal shield connection trenches 105-1 and 105-2, and the third section of the corresponding trench 101 below the horizontal shield connection trench 105-2 may share a common y-axis (eg, axis Yt) and are not staggered relative to each other in the x-direction). For example, FIG. 6 shows trench segment 101-U, horizontal shield connection trench 105-1 of trench 101 above horizontal shield connection trench 105-1 all aligned on a common y-axis (ie, Yt). The trench section 101-M of the trench 101 between the trench 105-2 and the trench section 101-L of the trench 101 below the horizontal shield connection trench 105-2. Similarly, adjacent segments of mesa 102 above, between, and below horizontal shield connection trenches 105-1 and 105-2 are all aligned on a common y-axis (ie, Ym). In device 600, as in device 200, above (eg, trench section 10-U), between (eg, trench section 10-M) horizontal shield connection trenches 105-1 and 105-2 ), and the corresponding segments of the active trench 101 (and the mesa 102 ) extending in the y-direction below (for example, trench segment 10-L) are aligned with each other in the x-direction, and are not in the x-direction staggered relative to each other.

In an example implementation, two horizontal shield connection trenches 105-1 and 105-2 may be used as regions to contact the shield polysilicon buried under the gate polysilicon in the device. For example, array 116A of insulator-lined conductive plugs 116 may be disposed in trench 105-1 and array 116B of insulator-lined conductive plugs 116 may be disposed in trench 105-2 to make shielded polysilicon contacts. Having two horizontal shield connection trenches 105-1 and 105-2 increases the number of shield contacts that can be fabricated in a device compared to using only a single shield connection trench. In an example implementation, the source metal 720 may be used to connect to shield contacts formed in the two horizontal shield connection trenches 105-1 and 105-2.

In an example embodiment, as previously described above with reference to device 200 ( FIGS. 2A-2C ), in device 600 , the shield connection trench 105 is deposited along one side or around the insulator-lined conductive plug 116 . The gate polysilicon in -1 and 105-2 can provide structural and electrical continuity to the gate electrode in trench 101 across shield connection trenches 105-1 and 105-2.

As previously described with reference to device 200, the buried shield polysilicon layer in device 600 may be lined by a vertical insulator fabricated as a through-shield connection to gate polysilicon layer 108 (FIG. 2A) in trenches 105-1 and 105-2. The arrays ( 116A and 116B ) of conductive plugs 116 make contacts. Each insulator-lined conductive plug 116 may be lined with an insulator (eg, oxide 110 of FIG. 2A ) to form internal opening 16 . Internal opening 16 may be filled with a conductive material (eg, conductive material 109 of FIGS. 2A-2C ) to contact the shield polysilicon underlying buried gate polysilicon 108 in device 600 . Gate polysilicon 108 disposed along and around vertical contact insulator lined conductive plug 116 maintains electrical continuity of the gate electrode formed in active trench 101 across shield connection trenches 105-1 and 105-2 in device 600 sex.

As mentioned above with reference to FIG. 6, in device 600, above (eg, trench section 10-U), between (eg, trench section 10-M), and corresponding segments of the active trench 101 (and mesa 102 ) extending in the y-direction below (for example, trench segment 10-L) are aligned with each other in the x-direction, and in the x-direction are not staggered relative to each other.

7 shows an example shielded gate trench MOSFET device 700 as device 600 with two shield connection trenches 105 - 1 and 105 - 2 intersecting the active trench 101 and the mesa 102 vertically. However, in device 700 , unlike device 600 , two shield connection trenches 105 - 1 and 105 - 2 are configured as termination trenches for a segment of active trench 101 . Furthermore, the section of active trench 101 (and mesa 102 ) extending in the y direction between the two horizontal shield connection trenches 105 - 1 and 105 - 2 (for example, trench section 10 -M ) is defined at x The direction is staggered with respect to the trench segments (eg, trench segments 10 -U and 10 -L) above and below the two horizontal shield connection trenches 105 - 1 and 105 - 2 . In FIG. 7, the stagger distance between different trench segments is indicated as the distance DS in the x-direction. In other words, the middle section longitudinal groove (eg, groove 101-M in groove section 10-M) is relative to the first section longitudinal groove and the second section longitudinal groove (eg, groove 101 -U and 101 -L) parallel to the first and second lateral trenches (eg, the horizontal shield connection trenches 105 - 1 and 105 - 2 ) are offset by a stagger distance DS. Staggering active trench segments avoids having to deal with large (4-way) trench intersections.

In an example embodiment, horizontal trenches (eg, shield connection trenches 105 ) to intercept and intersect (i.e., truncate) trenches 101 and mesas 102 to create regions for making shielded polysilicon contacts may include A plurality of short length discrete trench segments each intersecting only a small number of trenches 101 and mesas 102 (eg, two to five trenches 101 ). Further, these short length horizontal trench segments can intersect a small number of trenches 101 at different locations in the device layout.

FIG. 8 shows an example shielded gate trench MOSFET device 800 in which short length horizontal trench segments vertically intersect and intersect a small number of active trenches to create side regions for making shielded polysilicon contacts.

Device 800 (eg, devices 600 and 700 ) may include active trenches 101 and mesas 102 running in the y-direction between two gate feeds. The two gate feeds are formed from two sheets or strips of gate metal (e.g., gate metal 710-1 and gate metal 710-2), which are connected to the gate in the end region of the active trench 101. Pole electrode contacts (eg, contacts 702 ).

The first short-length shield connection trench 105-3 is located laterally across trenches 101-1, 101-2, and 101-c (and mesas 102-1 and 102-2) at approximately position Y1 on the y-axis (for example, in the x-direction) extend. The second, short-length shield connection trench 105-4 is located laterally across trenches 101-c, 101-3, and 101-4 (and mesas 102-3 and 102-3) at approximately position Y2 on the y-axis. (for example, in the x-direction) extend.

As shown in FIG. 8, the short-length shield connection trenches 105-3 effectively divide each of the longitudinal trenches 101-1 and 101-2 and each of the mesas 102-1 and 102-2 into two sections (for example, the upper The section is in the upper region (eg, region 12U) above the shield connection trench 105-3 in the y-direction, and the lower section is in the lower region (eg, region 12U) below the shield connection trench 105-3 in the y-direction. 12L). The short-length shield connection trenches 105-4 effectively divide each of the longitudinal trenches 101-3 and 101-4 and each of the mesas 102-3 and 102-4 into two sections (e.g., where the upper section is in the y direction in the upper region (eg, region 14U) above the shield connection trench 105 - 4 , and the lower section is in the lower region (eg, region 14L) below the shield connection trench 105 - 4 in the y-direction).

The short length shield connection trenches 105 - 3 and 105 - 4 can accommodate only a limited number of insulator lined conductive plugs 116 for making shield polysilicon contacts in device 800 due to their limited length or area. For example, array 116C and array 116D, each comprising two insulator-lined conductive plugs 116, may be disposed in short-length shield connection trenches 105-3 and 105-4, respectively. However, the diversity of locations in which short length shield connection trenches 105-3 and 105-4 can be used (e.g., locations Y1 and Y2) and the consequent insulator lining for making shield polysilicon contacts The variety in the location of the conductive plug 116 can result in device design flexibility and processing robustness.

In an example implementation, a MOSFET device includes a set of vertical trenches and vertical mesas extending longitudinally across a semiconductor substrate from a gate feed. The device further includes a first lateral trench perpendicularly intersecting at least one of the set of longitudinal trenches and the longitudinal mesa at a first distance from the gate feed, the first lateral trench in fluid communication with the at least one of the set of longitudinal trenches intersected; and a second lateral trench in the semiconductor substrate at a second distance from the gate feed to the set of longitudinal trenches At least one of the grooves and the longitudinal mesas perpendicularly intersect, the second lateral groove being in fluid communication with the at least one of the intersecting set of longitudinal grooves.

In the MOSFET device, a shielding polysilicon layer is disposed in the set of vertical trenches and the first and second lateral trenches. An interpoly dielectric (IPD) and a gate polysilicon layer are disposed over the shielding polysilicon layer in the set of vertical trenches and the lateral trenches.

Further, in the MOSFET device, a first electrical contact to the shielding polysilicon layer is made through one of the interpolysilicon dielectric layer and the gate polysilicon layer disposed in the first lateral trench A first insulator lined conductive plug is made and a second electrical contact to the shield polysilicon layer is made through the interpoly dielectric layer and the gate polysilicon layer disposed in the second lateral trench A second insulator lined with a conductive plug is made.

In the MOSFET device, the gate polysilicon disposed in at least one of the set of vertical trenches intersecting the first lateral trench forms an electrical contact not interrupted by the shielding polysilicon layer A continuous gate electrode of the device, the electrical contact being made by the first insulator lined conductive plug through the interpoly dielectric layer and the gate polysilicon layer disposed in the first lateral trench become. The gate polysilicon disposed in at least one of the set of longitudinal trenches intersecting the second lateral trench also forms a continuation of the device uninterrupted by the electrical contact to the shielding polysilicon layer A gate electrode, the electrical contact being made by the first insulator-lined conductive plug through the interpolysilicon dielectric layer and the gate polysilicon layer disposed in the second lateral trench.

In some example implementations of the MOSFET device, the at least one of the set of longitudinal trenches that intersects the first lateral trench at the first distance is the same as the second side trench at the second distance. The at least one longitudinal groove that intersects the grooves is a different one of the set of longitudinal grooves.

In some example implementations of the MOSFET device, the at least one of the set of longitudinal trenches that intersects the first lateral trench at the first distance is the same as the second side trench at the second distance. The ones of the set of longitudinal grooves intersecting toward the grooves are identical.

In some example implementations of the MOSFET device, one of the set of longitudinal trenches that intersects the first lateral trench at the first distance and intersects the second lateral trench at the second distance The at least one is divided into a first section longitudinal groove on one side of the first lateral section, an intermediate section side between the first lateral groove and the second lateral groove towards the groove, and a third section longitudinal groove on one side of the second lateral groove. In some example embodiments of the device, the intermediate section longitudinal groove is parallel to the first lateral groove and the second lateral groove relative to the first section longitudinal groove and the second section longitudinal groove. The grooves are offset by a stagger distance.

FIG. 9 shows an example method 900 for reducing shield electrode resistance in a shielded gate trench MOSFET device.

Method 900 includes defining a plurality of trenches of a first type in a semiconductor substrate (910). The plurality of trenches of the first type extend in a longitudinal direction (eg, extend from a gate feed region). Method 900 further includes defining a trench of a second type extending in a lateral direction and intersecting the plurality of trenches of the first type (920), the trench of the second type intersecting Each of the plurality of grooves of the first type are in fluid communication. Method 900 further includes disposing (930) a shielding polysilicon layer in the plurality of trenches of the first type and the trenches of the second type; disposing an interpolysilicon dielectric layer (IPL) and a gate polysilicon layer over the shielding polysilicon layer in the trench (940); and forming an electrical contact to the shielding polysilicon layer through An opening in the interpoly dielectric layer and the gate polysilicon layer in the trench of the second type (950).

In method 900, forming the electrical contact to the shielding polysilicon layer through the opening includes lining the opening with an insulator (eg, an oxide) and disposing a metal (eg, tungsten), a metal alloy, a metal silicide, or conductive polysilicon.

A method includes: defining a plurality of trenches of a first type in a semiconductor substrate, the plurality of trenches of the first type extending in a longitudinal direction; defining a trench of a second type with a extending in a lateral direction and intersecting the plurality of grooves of the first type, the grooves of the second type being in fluid communication with each of the intersecting first type of the plurality of grooves; A shielding polysilicon layer is disposed in the plurality of trenches of the first type and the trenches of the second type; an interpolysilicon dielectric layer is disposed in the plurality of trenches of the first type and the trenches of the second type (IPL) and a gate polysilicon layer disposed over the shield polysilicon layer; and formed through an opening in the interpoly dielectric layer and the gate polysilicon layer disposed in the trench of the second type to An electrical contact of the shielding polysilicon layer.

In the foregoing method, forming the electrical contact to the shield polysilicon layer through the opening includes lining the opening with an insulator.

In the foregoing method, forming the electrical contact to the shielding polysilicon layer through the opening includes disposing one of a metal, a metal alloy, a metal silicide, or conductive polysilicon in the opening.

In the foregoing method, forming the electrical contact to the shield polysilicon layer through the opening includes disposing tungsten in the opening.

Specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Example embodiments may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.

It will be understood that the specific number and geometric size and distribution of electrical contacts in the shield connection trenches are not limited to what is shown in the drawings herein.

For example, representative embodiments depicted in the figures herein may include a specific number and geometry and alignment of electrical contacts (eg, via insulator-lined conductive plugs 116 ) in shield connection trenches. For example, the representative embodiments depicted in the drawings show one electrical contact in the shield connection trench for each mesa, or for every two mesas, having a width comparable to the width of one mesa or the width of two mesas. Width electrical contacts, and electrical contacts that are usually geometrically aligned with the mesa, etc. Other embodiments within the scope of the present disclosure are not necessarily limited to the representative embodiments shown in the drawings herein. For example, other embodiments may include electrical contacts aligned with the inter-mesa trenches, or partially aligned with the mesa and the inter-mesa trenches, or randomly positioned in the shield connection trenches regardless of alignment with the mesas or the inter-mesa trenches. pieces. For example, other embodiments may include electrical contacts having any width that need not be an integer multiple or integer fraction of the mesa width (or inter-mesa trench width). Similarly, for example, other embodiments may include a number of contacts in a shield connection trench that is not an integer multiple or an integer fraction of the number of mesas (or trenches between mesas).

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN) , and/or etc.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms "a, an" and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that when the terms "comprise/comprising" and/or "include/including" are used in this specification, it indicates the existence of said features, steps, operations, elements, and/or components, But it does not exclude the existence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.

It will also be understood that when an element (such as a layer, region, or substrate) is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, its It can be directly on, connected or coupled to another element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on (directly on), directly connected to (directly connected to), or directly coupled to (directly coupled to) may not be used throughout the embodiments, they may be displayed as directly on, directly A component that is connected to, or directly coupled to. The claims of this application may be amended to recite the illustrative relationships described in this specification or shown in the drawings.

When used in this specification, a singular form may include a plural form unless a specific case is clearly indicated in the context. In addition to the orientation depicted in the drawings, spatially relative terms (e.g., over, above, upper, under, beneath, below, below ( lower), etc.) are intended to cover different orientations of the device in use or in operation. In some embodiments, the relative terms above and below include vertically above and below, respectively. In some embodiments, the term adjacent can include laterally adjacent or horizontally adjacent.

Example implementations of inventive concepts are described herein with reference to cross-sectional drawings that are schematic illustrations of idealized implementations (and intermediate structures) of example implementations. As such, variations in shape from the drawings may be expected as a result, for example, of manufacturing techniques and/or tolerances. Thus, example embodiments of the inventive concept should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Accordingly, the regions depicted in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example implementations.

It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a "first" element could be termed a "second" element without departing from the teachings of the present embodiments.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the inventive concept belongs. It should be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted to have a meaning consistent with their meaning in the context of the relevant art and/or this specification, and will not be in an idealized or overly formal sense read, unless expressly so defined herein.

While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments. It should be understood that these are presented by way of example only (not limitation), and that various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or subcombinations of the functions, components, and/or features of the different implementations described.

10L: Lower area 10M: middle area 10U: Upper area 11: Arrow 12: Arrow 12L: area 12U: area 14L: area 14U: area 16: Internal opening 100:Device Mask Layout 101: Groove 101-1: groove 101-2: groove 101-3: Groove 101-4: Groove 101-c: Trench 101-L: Groove section 101-M: Trench Section 101-U: Trench Section 102: Mesa 102-1: Mesa 102-2: Mesa 102-3: Mesa 102-4: Mesa 103: Source contact area 104: section 105: Shield connection groove 105-1: groove 105-2: groove 105-3: groove 105-4: groove 106: opening 106A: array 107:Gate oxide 108: Gate polysilicon layer 109: Conductive material 110: oxide 111: Buried shielding polysilicon layer 112: Inter-polysilicon dielectric (IPD) layer 113: oxide layer 116: Insulator lined with conductive plug 116A: array 116B: array 116C: array 116D: array 200: Shielded Gate Trench MOSFET Device 300: Shielded Gate Trench MOSFET Devices 400: Shielded Gate Trench MOSFET Devices 500: Shielded Gate Trench MOSFET Devices 600: Shielded Gate Trench MOSFET Devices 700: Shielded Gate Trench MOSFET Devices 702: contact piece 710-1: Gate metal 710-2: Gate metal 720: source metal 800: Shielded Gate Trench MOSFET Devices 900: method 910: step 920: step 930: step 940: step 950: step

[FIG. 1] depicts a portion of an example device mask layout. [FIG. 2A] depicts a portion of an example shielded gate trench MOSFET device. [ FIG. 2B ] is a cross-sectional view of a part of the device shown in FIG. 2A . [FIG. 2C] Another cross-sectional view showing a part of the device of FIG. 2A. [FIG. 3] shows another example shielded gate trench MOSFET device. [FIG. 4] shows yet another example shielded gate trench MOSFET device. [FIG. 5] shows a further example shielded gate trench MOSFET device. [FIG. 6] shows yet another example shielded gate trench MOSFET device. [FIG. 7] shows an additional example shielded gate trench MOSFET device. [FIG. 8] illustrates yet another additional example shielded gate trench MOSFET device. [Fig. 9] shows an example method.

10L: Lower area

10M: middle area

10U: Upper area

16: Internal opening

101: Groove

101-L: Groove section

101-M: Trench Section

101-U: Trench Section

102: Mesa

103: Source contact area

105-1: groove

105-2: groove

106: opening

108: Gate polysilicon layer

116A: array

116B: array

600: Shielded Gate Trench MOSFET Devices

702: contact piece

710-1: Gate metal

710-2: Gate metal

720: source metal

Claims (11)

A device comprising: a plurality of trenches of a first directional type in a semiconductor substrate, the plurality of trenches of the first directional type extending in a longitudinal direction; a groove of a second directional type extending in a lateral direction and intersecting the plurality of grooves of the first directional type, the grooves of the second directional type intersecting the intersected grooves of the first directional type each of the plurality of grooves is in fluid communication, the longitudinal direction being normal to the transverse direction; a shielding polysilicon layer disposed in the plurality of trenches of the first orientation type and the trenches of the second orientation type; an interpolysilicon dielectric layer (IPL) and a gate polysilicon layer disposed over the shield polysilicon layer in the plurality of trenches of the first orientation type and the trenches of the second orientation type; and An electrical contact to the shield polysilicon layer is disposed within an opening in the interpoly dielectric layer and the gate polysilicon layer disposed in the trench of the second orientation type. The device of claim 1, wherein the electrical contact to the shielding polysilicon layer is an insulator lined conductive plug disposed in an opening in the interpolysilicon dielectric layer and the gate polysilicon layer, the insulator The lined conductive plug is an oxide lined conductive plug. The device according to claim 1, wherein a continuous gate electrode of the device is formed through the gate polysilicon layer disposed in the plurality of trenches of the first direction type, and the continuous gate electrode is not formed by being disposed in the plurality of trenches The electrical contact to the shield polysilicon layer is interrupted within the opening in the interpoly dielectric layer and the gate polysilicon layer disposed in the trench of the second orientation type. A device comprising: A plurality of longitudinal trenches and longitudinal mesas of a first directional type extending parallel in a longitudinal direction across a semiconductor substrate; A lateral groove of a second direction type extending in a transverse direction perpendicular to the longitudinal direction and perpendicularly intersecting the plurality of longitudinal grooves and longitudinal mesas of the first direction type, the lateral groove The groove is in fluid communication with the plurality of longitudinal grooves of the first direction type, the lateral groove dividing each of the plurality of longitudinal grooves and the longitudinal mesas into a second groove on a first side of the lateral groove. a segmental longitudinal groove and a first segmental mesa and a second segmental longitudinal groove and a second segmental longitudinal mesa on a second side opposite the first side of the lateral groove, the lateral groove is in fluid communication with each of the first and second section longitudinal grooves; a shielding polysilicon layer disposed in the plurality of longitudinal trenches and the lateral trenches; an interpolysilicon dielectric layer (IPL) and a gate polysilicon layer disposed over the shield polysilicon layer in the plurality of vertical trenches and the lateral trenches; and an electrical contact to the shield polysilicon layer made of at least one insulator lined conductive plug extending through the interpoly dielectric layer and the gate disposed in the lateral trench polysilicon layer. The device of claim 4, wherein the at least one insulator-lined conductive plug, a first segment longitudinal mesa, and a second segment longitudinal mesa are aligned along a common longitudinal axis perpendicular to the lateral trench allow. The device of claim 4, wherein each of the plurality of longitudinal trenches and longitudinal mesas has a trench width and a mesa width, and wherein the at least one insulator-lined conductive plug has a width that is: the same or Less than the mesa width or greater than the mesa width. The device of claim 4, wherein the at least one insulator-lined conductive plug includes a plurality of insulator-lined conductive plugs disposed in the lateral trench, and the number of the insulator-lined conductive plugs is the plurality About the same number or about half the number of longitudinal grooves in the longitudinal grooves. The device of claim 4, wherein the at least one insulator-lined conductive plug in the interpoly dielectric and the gate polysilicon layer disposed in the lateral trench is disposed in a first section In a space between the table top and the table top of a second section. The device according to claim 4, wherein a continuous gate electrode of the device is formed through the gate polysilicon layer disposed in the plurality of vertical trenches and the lateral trenches, and the continuous gate electrode is not provided by passing through The electrical contact to the shield polysilicon layer is interrupted by the at least one insulator-lined conductive plug in the interpolysilicon dielectric layer and the gate polysilicon layer in the lateral trench. A method comprising: defining a plurality of trenches of a first type in a semiconductor substrate, the plurality of trenches of the first type extending in a longitudinal direction; defining a groove of a second type extending in a lateral direction and intersecting the plurality of grooves of the first type, the grooves of the second type intersecting the plurality of grooves of the first type Each of the grooves is in fluid communication; disposing a shielding polysilicon layer in the plurality of trenches of the first type and the trenches of the second type; disposing an interpolysilicon dielectric (IPD) and a gate polysilicon layer over the shield polysilicon layer in the plurality of trenches of the first type and the trenches of the second type; and An electrical contact to the shield polysilicon layer is formed through an opening in the interpolysilicon dielectric layer and the gate polysilicon layer disposed in the trench of the second type. The method of claim 10, wherein forming the electrical contact to the shielding polysilicon layer through the opening includes lining the opening with an insulator.

Images