KR20230159452A - Shield contact layout for power MOSFETs - Google Patents

Abstract

The method includes forming a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-) of a first type extending longitudinally in a semiconductor substrate. U), and laterally extending, a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M) of a first type. , 101-U) and defining a second type of trench (105, 105-1, 105-2, 105-3, 105-4). The second type trenches (105, 105-1, 105-2, 105-3, 105-4) are formed by crossing a plurality of trenches (101, 101-1, 101-2, 102-3, 10) of the first type. -4, 101-c, 101-L, 101-M, 101-U) are in fluid communication with each. The method includes a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of a first type and a trench of a second type. disposing a shielding poly layer (111) in (105, 105-1, 105-2, 105-3, 105-4) a plurality of trenches (101, 101-1, 101-2, 102) of a first type; -3, 10-4, 101-c, 101-L, 101-M, 101-U) and shielding in trenches of the second type (105, 105-1, 105-2, 105-3, 105-4) Disposing an inter-poly dielectric layer (112) and a gate poly layer (108) over the poly layer (111), and the inter-poly dielectric layer (112) and gate poly layer (108) disposed in a second type of trench. It further includes forming electrical contact to the shielding poly layer (111) through the openings (106, 16) in the inner layer (111).

Description

Shield contact layout for power MOSFETs

Cross-reference to related applications

This application claims priority and benefit of U.S. Provisional Patent Application No. 63/166,242, filed March 26, 2021, and the priority and benefit of U.S. Provisional Application No. 17/655,579, filed March 21, 2022. The benefit of which is claimed is hereby incorporated by reference in its entirety.

This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63/166,242, filed March 26, 2021, the entirety of which is incorporated herein by reference.

Technology field

This discussion relates to contacts in a shielded gate trench MOSFET.

Buried polysilicon shielding electrodes are used in shielded gate trench MOSFETs for charge balancing and to reduce the drain-source on resistance (RDS _on ) of the device. However, the resistance and stray capacitance associated with polysilicon shielding electrodes can affect the electrical performance of the device by, for example, causing undesirable gate bounce or low avalanche capability during unclamped inductive switching (UIS) in the device circuitry. This may affect performance or otherwise affect application efficiency. As semiconductor devices (e.g. device cell dimensions) and lithography design rules shrink, low-resistance buried features in semiconductor devices (e.g. shielded gate trench MOSFETs), for example, to prevent or reduce gate bounce and poor avalanche capabilities. Making polysilicon shielding electrodes is becoming increasingly difficult.

In a general aspect, a device includes a plurality of trenches of a first direction type extending longitudinally in a semiconductor substrate, and trenches of a second direction type extending laterally and intersecting the plurality of trenches of the first direction type. The longitudinal direction is perpendicular to the transverse direction. A trench of the second direction type is in fluid communication with each of the plurality of trenches of the first direction type intersected.

The device includes a shielding poly layer disposed in the plurality of trenches of the first direction type and the trenches of the second direction type, a poly-interlayer disposed over the shielding poly layer in the plurality of trenches of the first direction type and the trenches of the second direction type ( and an inter-poly dielectric layer (IPL) and a gate poly layer, and electrical contact to a shielding poly layer disposed within an opening in the inter-poly dielectric layer and the gate poly layer disposed in the trench of the second direction type.

In a general aspect, a device includes a plurality of longitudinal trenches and longitudinal mesas of a first direction type extending longitudinally parallel across a semiconductor substrate, and a plurality of longitudinal trenches and longitudinal mesas of a first direction type extending transversely orthogonal to the longitudinal direction. It includes a longitudinal trench and a second directional type of lateral trench perpendicularly intersecting the longitudinal mesa. The lateral trench is in fluid communication with a plurality of longitudinal trenches of the first directional type. The lateral trench includes a plurality of longitudinal trenches and a longitudinal mesa, respectively, on a first section longitudinal trench and a first side of the lateral trench and a second section longitudinal trench and a second section on a first side of the lateral trench. A second section on the second opposite side is divided by a longitudinal mesa. The lateral trench is in fluid communication with each of the plurality of first section longitudinal trenches and the plurality of second section longitudinal trenches.

The device includes a shielding poly layer disposed in a plurality of longitudinal trenches and lateral trenches, an inter-poly dielectric layer (IPL) and a gate poly layer disposed over the shielding poly layer in the plurality of longitudinal trenches and lateral trenches, and a gate poly layer in the plurality of longitudinal trenches and lateral trenches. It further includes electrical contact to the shielding poly layer by at least one insulator-lined conductive-plug extending through the inter-poly dielectric layer disposed in the trench and the gate poly layer.

In a general aspect, the method includes defining a plurality of trenches of a first type in a semiconductor substrate. The plurality of trenches of the first type extend longitudinally. The method further includes defining a second type of trench that extends laterally and intersects the plurality of trenches of the first type. The trenches of the second type are in fluid communication with each of the plurality of trenches of the first type crossed. The method includes disposing a shielding poly layer in the plurality of trenches of the first type and the trenches of the second type, forming an inter-poly dielectric layer (IPD) over the shielding poly layer in the plurality of trenches of the first type and the trenches of the second type. and disposing a gate poly layer, and forming electrical contact to the shielding poly layer through the opening in the gate poly layer and the inter-poly dielectric layer disposed in the second type of trench.

1 illustrates a portion of an example device mask layout.
2A illustrates a portion of an example shielded gate trench MOSFET device.
FIG. 2B is an illustration of a cross-sectional view of a portion of the device of FIG. 2A.
Figure 2C is an illustration of another cross-sectional view of a portion of the device of Figure 2A.
3 illustrates another example shielded gate trench MOSFET device.
4 is an illustration of another exemplary shielded gate trench MOSFET device.
5 is an illustration of a further exemplary shielded gate trench MOSFET device.
6 is an illustration of another exemplary shielded gate trench MOSFET device.
7 is an illustration of a further exemplary shielded gate trench MOSFET device.
8 is an illustration of another additional exemplary shielded gate trench MOSFET device.
9 is an illustration of an exemplary method.

Metal oxide semiconductor field effect transistor (MOSFET) devices are used in many power switching applications. In a typical MOSFET device, the gate electrode provides turn-on and turn-off control of the device in response to an applied gate voltage. For example, in an N-type enhancement mode MOSFET, the conductive N-type inversion layer (i.e., the channel region) responds to a positive gate voltage exceeding its intrinsic threshold voltage, causing p- Turn-on occurs when the shape is formed in the body region. The inversion layer connects the N-type source region to the N-type drain region and enables majority carrier conduction between these regions.

In a trench MOSFET device, the gate electrode is formed in a trench that extends downward (e.g., vertically downward) from the main surface (also referred to as a semiconductor region) of a semiconductor material, such as silicon. Additionally, a shielding electrode can be formed below the gate electrode in the trench (and insulated via an inter-electrode or inter-poly dielectric). Current flow in a trench MOSFET device is primarily vertical (e.g., in the N-doped drift region), resulting in the device cells being more densely packed. The device cell may include, for example, a trench containing a gate electrode and a shielding electrode, and an adjacent mesa containing the drain, source, body and channel regions of the device.

The current handling ability of a trench MOSFET device is determined by its gate channel width. To minimize cost, the die area size of the transistor is kept as small as possible and the width of the channel surface area is increased (i.e., "channel density") by creating repeated cellular structures across the entire area of the MOSFET die. increasing) may be important. A way to increase channel density (and thus increase channel width) is to reduce the size of the device cells and pack more device cells at a smaller pitch for a given surface area.

An exemplary trench MOSFET device may include an array of hundreds or thousands of device cells, each containing a trench and adjacent mesa. The device cells may be referred to herein as trench-mesa cells because each device cell geometrically includes a trench and a mesa (or two half mesa) structures. The shield and gate electrode may be formed inside a linear trench (e.g., trench 101) extending along (e.g., aligned along) a mesa (e.g., mesa 102). The shield and gate electrode may be made of polysilicon (e.g., “n+ shield polysilicon” and “n+ gate polysilicon”) and attached to a dielectric layer (e.g., interpoly-dielectric (IPD) layer 112, FIG. 2B). can be insulated from each other. The IPD layer may be, for example, an oxide layer. The shield and gate electrodes are also insulated from the silicon in the mesa by dielectric layers (eg, shield dielectric and gate dielectric layers).

To ensure proper electrical contact of all cells, a "planar stripe" structure is often used for trench MOSFETs fabricated on the surface of a semiconductor die. In a planar stripe structure, the gate electrode (“gate”) and shielding electrode (“shielding poly”) within a trench (e.g., a linear trench) extend along (e.g., aligned along) the length of the trench in a longitudinal stripe. ) is placed. A trench containing a gate electrode and a shielding electrode may be referred to as an active trench. A gate electrode (e.g., made of gate poly) is disposed along the length of the active trench on top of (or on) a shield electrode (e.g., made of shield poly). The gate poly within the active trench is exposed and contacted at the stripe ends by gate runners (e.g., gate metal), and the shielding electrode (shielding poly) within the trench is positioned along the length of the active trench for contact by the source metal. can be exposed to and lifted onto a surface (using a masking step).

In modern trench MOSFET devices (i.e., those with narrow feature widths), shielding resistance is a factor that affects device efficiency and performance. Low shielding resistance is achieved by making multiple contacts to the shielding poly in the active trench (e.g., by raising the shielding poly vertically to the surface through the gate poly at multiple locations, making multiple shielding contacts with the source metal). You can get it.

Raising the shielding poly vertically to the surface (from directly below the gate poly) disrupts or breaks the continuity of the gate poly extending along the length of the active trench. The gate poly is divided into two discontinuous segments along the length of the active trench with each instance of a shielding poly raised vertically to the surface. In an exemplary implementation, two separate gate runners or gate metal strips (e.g., gate metals 710-1 and 710-2, shown in FIGS. 6 and 7) at the ends of the stripes. , may be required to contact two disconnected gate poly segments created by a single instance of the shielding poly raised vertically to the surface through the active trench. Multiple instances of shielding poly raised vertically to the surface through the gate poly along the length of the active trench, with several isolated gate poly segments floating (i.e. not connected by two separate gate runners). This can result in multiple gate runners making contact with each gate poly segment that occupies the die area.

The disclosure herein describes an exemplary device configuration or layout for making contact to a shielding electrode buried beneath a gate electrode in the active trench of a MOSFET device fabricated within a semiconductor substrate. Contacts (e.g., metal, metal alloy, metal silicide, conductive poly, or other conductive material contacts) are made to shield the buried poly below the gate poly in the shield-connected trench perpendicular to and crossing the active trench. The shield connection trench may be a portion of the trench to the side of the active trench. The contact is a vertical insulator-lined (e.g., oxide-lined) opening extending from the top surface through the gate poly (and other dielectric (e.g., interlayer dielectric)) overlaying the shield electrode to reach the buried shield poly. It is created through The embedded shielding poly remains beneath the gate poly and is not raised to the surface. Instead, contact is made to the shielding poly by depositing a conductive material (e.g. metal, tungsten) in the opening. The gate poly is routed in a horizontal plane around the opening in the shield-connected trench to maintain continuity of the gate electrode in a portion of the active trench on one side of the contact and a corresponding portion of the active trench on the opposite side of the contact.

1 shows an example device mask layout 100 of a shielded gate trench MOSFET device (e.g., device 200, FIGS. 2A, 2B, and 2C) in which multiple contacts can be made to the shield electrode within the device. Shows a part of . 1 shows, for example, a device mask layout 100 in the x-y plane (the x-y plane may be aligned along the plane of a silicon wafer or semiconductor substrate of a transistor device).

For ease of explanation, the relative orientations or coordinates of features (e.g., trenches 101 and 105, mesa 102, etc.) of the disclosed trench MOSFET device are, for example, the x and y axes shown on the page of FIG. May be described herein with reference to axes. A direction perpendicular to the x-y plane of the page (e.g., z-axis) may be referred to as a vertical direction or axis. The z direction may be downward into the depth of the semiconductor substrate and may be aligned with the depth of the trench, for example, in a MOSFET device fabricated within the semiconductor substrate. Additionally, for visual clarity, a limited number of trench/device cells (eg, 3 to 5 trench/device cells) of the array of trench/device cells within device mask layout 100 are shown in FIG. 1 . As previously discussed, an actual MOSFET device may include an array of hundreds or thousands of trench/device cells, e.g., using the limited array structure shown in example device mask layout 100 (e.g., x direction) can be obtained by repeating.

As shown in FIG. 1, device mask layout 100 includes a plurality of active trenches (i.e., longitudinal trenches) of the device extending parallel (e.g., substantially parallel) to each other (e.g., in the y direction). It includes a trench 101). Mesa 102 may be formed between pairs of longitudinal trenches 101 . Trench 101 and mesa 102 may be a linear trench and a linear mesa (eg, extending in the y direction), respectively. Trench 101 and mesa 102 may each have uniform widths (Wt and Wm) (e.g., horizontal width in the x-direction). Device elements (e.g., source and body regions (not shown)) may be formed in mesa 102 and may be contacted by a source metal (not shown), for example, in source contact region 103. Device elements (e.g., source and body regions) may be formed, for example, by n-type source and drain (NSD) implantation into sections 104 of device mask layout 100.

Although only a few trenches 101 and mesas 102 (e.g., four trenches and three mesas) are shown in Figure 1 (and other figures herein), an actual MOSFET device may, for example, be as shown in the figure. It should be noted that it may comprise an array of hundreds or thousands of trench/device cells, which may be obtained by repeating trench and mesa structures or patterns (e.g., in the x-direction).

Horizontal or lateral trenches (e.g., shield-connected trenches 105) (lateral trenches) extend laterally (e.g., in the x direction) and form trenches 101 and It is possible to intercept and traverse (i.e. traverse) the mesa 102. The shield-connection trench 105 may have a vertical width (Wv) in the y direction, for example. Shield-connected trench 105 may effectively divide each longitudinal trench 101 and each mesa 102 into two sections (e.g., the upper section of longitudinal trench 101 is in an upper region (e.g., region 10U) of device mask layout 100 above shield-connect trench 105, and the lower section of trench 101 is below shield-connect trench 105 in the y direction. In the lower region of device mask layout 100 (e.g., region 10L). The trenches (i.e., trench 101 and trench 105) may have approximately the same depth (not shown), for example, referenced from the top surface of mesa 102.

In an exemplary embodiment, there are two sections of longitudinal trench 101 on either side (i.e., above and below) of shield-connected trench 105 (i.e., longitudinal trench 101 in upper region 10U). The upper section of , and the corresponding lower section of trench 101 in lower region 10L) may be aligned in the horizontal may share or lie on a common y-axis (Yt) for vertical trenches).

Shield-connected trench 105 may be in fluid communication with each of the divided sections of trench 101 (i.e., shield-connected trench 105 has a physical opening to each divided section of trench 101, thereby allowing fluid (i.e., a gas or liquid that is not of fixed shape) can readily flow through the openings from the shield-connected trench 105 into each of the split sections of trench 101 and vice versa). The device's shield and gate electrodes (not shown) may be formed in trench 101, for example, by depositing shield poly and gate poly in trenches 101 and 105. The shield poly and gate poly may be separated by an inter-poly dielectric (IPD) layer (not shown in Figure 1).

The shield poly in the shield-connect trench 105 has one or more openings (e.g., openings 106 )) can be exposed to make contact to the shielding electrodes in the trenches 101 and 105. In an example implementation, an insulator-lined conductive plug (e.g., insulator-lined conductive plug 116 shown at least in FIGS. 2A, 2B, and 2C) may be fabricated within opening 106. The insulator-lined conductive-plug 116 has, for example, a conductive central portion made of conductive material 109 (Figure 2a) surrounded by a concentric insulating outer portion (made of oxide 110 (Figure 2a)). It can be included.

In an example implementation, referring again to device mask layout 100 (FIG. 1), openings 106 may first be filled with an oxide (e.g., oxide 110, FIG. 2A) or other insulator, and then Another opening may be made through oxide or other insulating filling, again forming an insulating-lined opening (e.g., opening 16) to reach the underlying shielding poly. In the device mask layout 100 shown in FIG. 1, these other insulator-lined openings (i.e., openings 16) are shown as dashed rectangles inside openings 106.

A metal or other conductive material (e.g., conductive material 109, Figure 2a) may be used to connect the underlying shield, e.g., for connection to a source metal of the device (e.g., source metal 720, Figures 6-9). It may be deposited on the oxide-lined opening 16 to establish electrical contact with the poly.

In an exemplary embodiment, the gate poly deposited in the shield-connected trench 105 along or about the side of the insulator-lined conductive-plug 116 formed in the opening 106 forms the shield-connected trench 105. ) (i.e., the gate poly within a section of trench 101 in upper region 10U may provide structural and electrical continuity of the gate electrode within trench 101 across regions 101). ) is continuous with the gate poly within the corresponding section of ).

In an exemplary embodiment, the openings 106 and 16 (and the insulator-lined conductive-plug(s) 116) have a square shape, a rectangular shape, a circular shape, an oval shape, or any other shape in the x-y plane. You can have it. In an example implementation, as shown in FIG. 1 , the opening 106 may have, for example, a rectangular shape with a width Wo in the x direction and a length Lo in the y direction. In example implementations, the width Wo may be greater than, equal to, or less than the width Wm of the mesa 102 .

In an exemplary implementation, for a MOSFET with a breakdown voltage (BVDSS) of 25 V to 30 V, trench 101 has a width (Wt), for example, in the range of about 0.2 μm to 1.0 μm (e.g., 0.3 μm). can have; Mesa 102 may have a width (Wm), for example, in the range of about 0.2 μm to 1.0 μm (eg, 0.3 μm); Shield contact trench 105 may have a width (Wv), for example, ranging from about 0.5 μm to 2.0 μm (eg, 1.0 μm); The insulator-lined conductive plug 116 may have a width (Wo) ranging from about 0.3 μm to 2.0 μm (e.g., 1.4 μm) and a length (Lo) ranging from about 0.3 μm to 1.2 μm (e.g., 0.6 μm); ; Contact opening 16 may have a width in the x-direction ranging from about 0.1 μm to 1.8 μm (eg, 1.0 μm) and a length in the y-direction ranging from about 0.1 μm to 1.0 μm (eg, 0.2 μm).

For MOSFETs with a breakdown voltage (BVDSS) greater than 30 V, the dimensions of the features described above (e.g., trench 101 width (Wt), mesa 102 width (Wm), shield contact trench 105 width (Wv) , the insulator-lined conductive plug 116 width (Wo) and length (Lo), and the contact opening 16 width and length) are the exemplary values given above for MOSFETs with a breakdown voltage (BVDSS) of 25 V to 30 V. It may be bigger than the numbers.

In an exemplary embodiment, an array of multiple openings 106 (e.g., array 106A) is disposed along the x-axis in shield-connected trench 105 to form insulator-lined conductive-plug(s) 116. A corresponding array 116A (FIG. 2A) can be formed.

In an exemplary embodiment, as shown in FIG. 2A, the insulator-lined conductive-plug 116 in the shield-connected trench 105 is connected to the mesa 102 of the upper region 10U and the mesa 102 of the lower region 10L. may be aligned in the y direction with a corresponding mesa 102 (i.e., insulator-lined conductive-plug 116, mesa 102 of upper region 10U, and corresponding mesa of lower region 10L ( 102) may all be arranged in the y direction along a common axis (e.g., axis Ym, Figure 2a).

FIG. 2A shows an example shielded gate trench MOSFET device 200 with a continuous gate electrode around the gate electrode uninterrupted (i.e., uninterrupted) by a shield contact made to shield the poly below the gate electrode. . In an example implementation, device 200 may be fabricated using device mask layout 100, for example. In the example shown in FIG. 2A , device 200 has active trenches 101 and mesa 102 extending in the y direction, and laterally across trenches 101 and mesa 102 (e.g., x direction) extending horizontal shield-connection trenches 105 (side trenches). Corresponding sections of the active trench 101 (and mesa 102) extending in the y direction above and below the horizontal shield-connected trench 105 may be aligned with each other in the x direction (i.e., the trench above ( The section of 101 and the corresponding section of trench 101 below may share a common y-axis (e.g., axis Yt) and may not be staggered relative to each other in the x-direction. 2A shows, for example, a section 101-U of trench 101 above horizontal shield-connected trench 105 and the corresponding trench 101 below aligned on a common y axis (i.e., Yt). A section 101-L is shown. Similarly, neighboring sections of mesa 102 above and below horizontal shield-connected trench 105 are aligned on a common y axis (i.e., (Ym)).

In an exemplary embodiment, the gate poly deposited in the shield-connected trench 105 along or about the sides of the insulator-lined conductive-plug 116 extends across the shield-connected trench 105 to form a trench 101 ) (i.e., the gate poly within a section of trench 101 in upper region 10U may provide structural and electrical continuity of the gate electrode in lower region 10U through shield-connected trench 105). continuous with the gate poly in the corresponding section of trench 101).

Gate oxide 107 may be grown or deposited on the sidewalls of mesa 102 adjacent to active trench 101 and shield-connected trench 105. A layer of gate poly 108 is deposited in active trench 101 and shield-connected trench 105, forming a layer of shield poly previously deposited in the trench (shield poly layer 111, FIG. 2B) and inter-poly. A gate electrode may be formed on the dielectric (IPD) layer 112 (IPD layer 112, FIG. 2B). The layer of shielding poly and the IPD layer are buried beneath the gate poly 108 and are therefore not visible in FIG. 2A.

In device 200, the buried shielding poly layer is an array of vertical insulator-lined conductive-plugs 116 (e.g. : is contacted by the array 116A). Each insulator-lined conductive-plug 116 may include a conductive central portion surrounded by an insulating liner. In an example implementation, the insulating liner may be made of an insulating material, such as oxide 110, and the conductive central portion may be made of a conductive material 109 (eg, tungsten). The conductive material 109 (e.g., tungsten) of each insulator-lined conductive-plug may be in electrical contact with a shielding poly buried beneath the gate poly 108 and IPD layer 112 within device 200. . Gate poly 108 along and around vertical insulator-lined conductive-plug 116 may maintain electrical continuity of the gate electrode formed in active trench 101 across shield-connected trench 105 .

Electrical contact to the buried shield poly layer is made between the gate poly layer 108 and the inter-poly dielectric layer 112 with at least one insulator-lined conductive-plug 116 disposed in the shield-connection trench 105. It is created by passing through and reaching the embedded shielding poly layer.

In an exemplary embodiment, the number of vertical insulator-lined conductive-plugs 116 in shield-connected trench 105 is greater than the number of active trenches 101 (or mesa 102) crossed by shield-connected trench 105. ) may be equal to (or approximately equal to) the number of Additionally, in an exemplary embodiment, as shown in FIG. 2A , the space between a section of mesa 102 in upper region 10A and a corresponding section of mesa 102 in lower region 10L each has An insulator-lined conductive-plug 116 may be disposed. Each insulator-lined conductive-plug 116 may have a rectangular shape with a width (Wo) in the x direction and a length (Lo) in the y direction. In an example implementation, as described above, the width Wo may be greater than, equal to, or less than the width Wm of the mesa 102. For example, in the example implementation shown in Figure 2A, the width (Wo) may be approximately 2 to 3 times greater than the length (Lo).

2B and 2C show cross-sectional views of a portion of device 200. 2B illustrates, for example, a portion of a section of mesa 102 in upper region 10A, a portion of a corresponding section of mesa 102 in lower region 10L, shield-connection trench 105, and insulator. A cross-sectional view (taken along line A-A in FIG. 2A in the z-y plane) is shown across the -lined conductive-plug 116 (disposed between mesas 102). The insulator-lined conductive-plug 116 includes a conductive central portion (e.g., conductive material 109) surrounded by a concentric insulating outer portion (e.g., oxide 110). 2B shows the insulator-lined conductive-plug 116 passing through gate poly 108 and IPD 112 to reach buried shielding poly layer 111 in shield-connection trench 105. The conductive material 109 (e.g., tungsten) of the conductive central portion of the insulator-lined conductive-plug 116 is in electrical contact with the buried shielding poly layer 111 in the shield-connection trench 105. Buried shielding poly layer 111 may be insulated from the bottom and sides of shield-connected trench 105 by a dielectric layer (eg, oxide layer 113).

FIG. 2C shows a cross-sectional view (taken along line B-B in FIG. 2A in the z-x plane) across, for example, a portion of the shield-connection trench 105 and two insulator-lined conductive-plugs 116. do. 2C shows, for example, two insulator-lined conductive-plugs 116 passing through gate poly 108 and IPD 112 and reaching buried shielding poly layer 111 in shield-connection trench 105. ) is shown. 2B, each of the two insulator-lined conductive plugs 116 includes a conductive central portion (e.g., conductive material 109) surrounded by a concentric insulating outer portion (e.g., oxide 110). Conductive material 109 (eg, tungsten) is in electrical contact with buried shielding poly layer 111 in shield-connected trench 105.

As described above, in the example implementation shown in FIG. 2A , corresponding sections of active trench 101 (and mesa 102) extend in the y direction above and below horizontal shield-connected trench 105. are aligned with each other in the x-direction and are not offset relative to each other in the x-direction. When shield-connected trench 105 and longitudinal trench 101 intersect without the sections becoming staggered, they create a four-way (x-y) intersection point of the trenches, as shown by arrows 11 in Figure 2A. can do.

3 shows another exemplary shielded gate having a continuous gate electrode around the gate electrode uninterrupted (e.g., uninterrupted) by a shield contact made to shield the poly below the gate electrode in a horizontal shield-connected trench. A trench MOSFET device 300 is shown. In device 300, corresponding sections of active trench 101 (and mesa 102) extending in the y-direction above and below horizontal shield-connected trench 105 have distances in the x-direction, for example. They are offset from each other in the x direction by (DS). Shield-connection trench 105 can act as a termination trench for staggered sections of longitudinal trench 101 and can be used in three directions (x-x-y) of the trench, as shown by arrows 12 in FIG. 3 . ) Intersection points can be created. Processing a 3-way intersection of a trench may be preferable to processing a 4-way intersection of a trench (arrow 11, FIG. 2A) under some processing conditions.

4 and 5 show another exemplary shielded gate trench MOSFET device (i.e. , device 400 and device 500, respectively) are shown. In device 400 and device 500, as in device 200, an active trench 101 (and mesa 102) extending in the y direction above and below horizontal shield-connected trench 105. Corresponding sections are aligned with each other in the x direction and are not staggered with respect to each other in the x direction. However, the number of vertical insulator-lined conductive-plugs 116 in the shield-connected trench 105 is greater than the number of active trenches 101 (or mesas 102) crossed by the shield-connected trench 105. You can write it down.

In an exemplary embodiment, the number of vertical insulator-lined conductive-plugs 116 in shield-connected trench 105 is greater than the number of active trenches 101 (or mesa 102) crossed by shield-connected trench 105. ) may be about half the number.

In the example implementation shown in FIG. 4 (device 400), each insulator-lined conductive-plug 116 may have a width (Wo) greater than the Wm of the mesa 102 (in the x direction). (e.g. Wo can be about twice as large as Wm). In an example implementation, Wo may be approximately equal to or greater than the sum of the width of mesa 102 (Wm) and the width of trench 101 (Wt). Additionally, in an exemplary embodiment, as shown in FIG. 4, each insulator-lined conductive-plug 116 has a section of a pair of mesas 102 in the upper region 10U and a section of the lower region 10L. ) may be disposed in the shield-connected trench 105 in the space between a pair of corresponding sections of a pair of mesas 102 in ). Each insulator-lined conductive-plug 116 may have a rectangular shape with a width (Wo) in the x direction and a length (Lo) in the y direction. In an example implementation, the width Wo may be greater than the width Wm of the mesa 102, as described above. For example, in the example implementation shown in FIG. 4, the width (Wo) may be approximately equal to the width of the two mesas (2Wm) and the width of the trench (Wt), i.e., Wo is 2*Wm + It may be approximately the same as Wt.

Figure 5 shows another example implementation of a device in which the number of vertical contact insulator-lined conductive-plugs 116 in the shield-connected trenches 105 is approximately half the number of active trenches 101. In device 500, each insulator-lined conductive-plug 116 may have a width (Wo) that is less than the width (Wm) of mesa 102 (in the x direction). Additionally, in an exemplary embodiment, as shown in FIG. 5, each insulator-lined conductive-plug 116 has sections of alternating mesas 102 in upper region 10A and lower region 10L. may be placed in the shield-connecting trench 105 in the space between corresponding sections of alternating mesas 102 in . That is, with respect to the first mesa 102, the opening insulator-lined conductive-plug is connected to a section of the first mesa 102 in the upper region 10U and a section of the first mesa 102 in the lower region 10L. may be arranged in the shield-connection trench 105 in the space between corresponding sections of; With regard to the second (neighboring) mesa 102 , the insulator-lined conductive-plug 116 is not disposed between the upper and lower sections of the second mesa 102 .

1-5, the longitudinal active trenches and mesas (e.g., trench 101 and mesa 102) extend longitudinally (e.g., along the y-axis or extends along the y direction). The longitudinal active trench and mesa may extend, for example, between two gate feeds (eg, gate metal 710-1 and gate metal 710-2, FIGS. 6-8). A plurality of longitudinal active trenches and mesas may be vertically traversed, for example, by a single horizontal shield connection trench 105, with a single linear array of insulator-lined conductive-plugs disposed in the shield connection trench 105. (e.g. array 116A) is used to make shielding contacts to the shielding poly within the device.

6, 7, 8, and 9 illustrate other example implementations, wherein the length between two gate feeds (e.g., gate metals 710-1 and 710-2, FIGS. 6-8) Directional active trenches and mesas (e.g., trenches 101 and 102) are vertically traversed by more than one horizontal shield-connection trench and are formed by more than one linear array of insulator-lined conductive-plugs (e.g., Array 116A) may be used to make shield contacts to shield polys in horizontal shield-connected trenches within the device.

Figure 6 shows another example shielded gate trench MOSFET device 600 with a continuous gate electrode around it unobstructed by a shield contact made to shield the poly under the gate electrode. In the example shown in FIG. 6 , device 600 includes an active trench 101 and a mesa 102 of the first direction type extending longitudinally (e.g., along the y direction) parallel between two gate feeds. ) includes. The two gate feeds are two gate feeds of gate metal (e.g., gate metal 710-1 and gate metal 710-2) connected to a gate electrode contact (e.g., contact 702) in the end region of active trench 101. It is formed by two sheets or strips.

The first horizontal shield-connecting trench 105-1 (side trench) of the second directional type extends laterally in the transverse direction (e.g., along the x direction) and approximately at a position Y1 on the y axis. Intersects trench 101 and mesa 102. The second horizontal shield-connection trench 105-1 (side trench) of the second direction type extends laterally in a transverse direction perpendicular to the longitudinal direction (e.g., along the x direction) and approximately on the y axis. Intersects trench 101 and mesa 102 at location Y2. Shield-connected trenches 105-1 and 105-2 may effectively divide each longitudinal trench 101 and each mesa 102 into three sections (e.g., shield-connected trench 105 A first section of the longitudinal trench 101 in a first region (e.g. upper region 10U) on the side of -1) (away from the side closer to the shield-connected trench 105-2 in y direction). , a second section of longitudinal trench 101 in a second region (e.g., intermediate region 10M) between shield-connected trenches 105-1 and 105-2 in the y direction, and a shield-connected trench. A third section of trench 101 in a third region (e.g., lower region 10L) on the side of 105-2 (away from the side closer to shield-connected trench 105-1 in the y direction). ). Source contact area 103 on mesa 102 in all three areas may be contacted, for example, by source metal 720.

Above (e.g., upper region 10U), between (e.g., middle region 10M), and sections of trench 101 and mesa 102 and horizontal shield-connected trenches 105-1 and 105-2. Corresponding sections of active trench 101 (and mesa 102) extending in the y-direction below (e.g., lower region 10L) may be aligned with each other in the x-direction (i.e., horizontal shield connection trench 105 -1) a first section of the trench 101 above, a second section of the trench 101 between the horizontal shield connection trenches 105-1 and 105-2, and below the horizontal shield connection trench 105-2 The third section of the corresponding trench 101 may share a common y-axis (e.g., axis Yt) and may not be staggered relative to each other in the x-direction. 6 shows, for example, a trench section 101-U of trench 101 above horizontal shield-connected trench 105-1, trench between horizontal shield-connected trenches 105-1 and 105-2 ( The trench section 101-M of 101 and the trench section 101-L of trench 101 below the horizontal shield-connected trench 105-2 are both aligned on a common y axis (i.e., Yt). It shows. Similarly, neighboring sections of mesa 102 above, between, and below horizontal shield-connected trenches 105-1 and 105-2 are all aligned on a common y axis (i.e., Ym). In device 600, as in device 200, above (e.g., trench section 10-U) or between (e.g., trench section 10) horizontal shield-connected trenches 105-1 and 105-2. -M)), and corresponding sections of active trench 101 (and mesa 102) extending in the y direction below (e.g., trench section 10-L) are aligned with each other in the x direction, and So they don't conflict with each other.

In an example implementation, both horizontal shield-connection trenches 105-1 and 105-2 may be used as areas for contacting a shield poly buried beneath the gate poly in the device. For example, array 116A of insulator-lined conductive-plugs 116 may be disposed in trench 105-1 and array 116B of insulator-lined conductive-plugs 116 may be disposed in the shielding poly. It may be placed in trench 105-2 to make contact. Having two horizontal shield-connection trenches 105-1 and 105-2 increases the number of shield contacts that can be made compared to the number of shield contacts that can be made in the device using only a single shield-connection trench. can increase. In an example implementation, source metal 720 may be used to connect shield contacts formed in two horizontal shield-connected trenches 105-1 and 105-2.

In an example implementation, as described above with reference to device 200 (FIGS. 2A-2C), in device 600, a shielding is provided along or around the sides of the insulator-lined conductive-plug 116. -Gate poly deposited in connection trenches 105-1 and 105-2 may provide structural and electrical continuity of the gate electrode in trench 101 across shield-connection trenches 105-1 and 105-2. .

As described above with reference to device 200, the buried shield poly layer within device 600 is connected through a layer of gate poly 108 (FIG. 2A) in shield-connected trenches 105-1 and 105-2. Contact may be made by arrays 116A and 116B of vertical insulator-lined conductive-plugs 116. Each insulator-lined conductive-plug 116 may be lined with an insulator (e.g., oxide 110, FIG. 2A) to form an interior opening 16. Internal opening 16 may be filled with a conductive material (e.g., conductive material 109, FIGS. 2A-2C) to contact a shielding poly buried under gate poly 108 in device 600. Gate poly 108 disposed along and around vertical contact insulator-lined conductive-plug 116 forms active trench 101 across shield-connected trenches 105-1 and 105-2 within device 600. ) maintains the electrical continuity of the gate electrode formed in

As described above with reference to FIG. 6 , at device 600, above (e.g., trench section 10-U) and between (e.g., trench sections) horizontal shield-connected trenches 105-1 and 105-2. (10-M)), and corresponding sections of active trench 101 (and mesa 102) extending in the y direction below (e.g., trench section 10-L) are aligned with each other in the x direction; They are not offset relative to each other in the x-direction.

7 shows an exemplary shielded gate trench MOSFET having two shield-connected trenches 105-1 and 105-2 perpendicularly intersecting active trench 101 and mesa 102, such as device 600. A device 700 is shown. However, in device 700, unlike device 600, two shield-connected trenches 105-1 and 105-2 are configured as termination trenches for sections of active trench 101. Additionally, a section of the active trench 101 (and mesa 102) extending in the y direction between two horizontal shield-connected trenches 105-1 and 105-2 (e.g., trench section 10-M). are staggered in the x-direction with respect to the trench sections above and below the two horizontal shield-connection trenches 105-1 and 105-2 (e.g., trench sections 10-U and 10-L). In Figure 7, the stagger distance between different trench sections is expressed as the distance in x direction (DS). That is, the middle section longitudinal trench (e.g., trench 101-M within trench section 10-M) is the first section and the second section longitudinal trench (e.g., trenches 101-U and 101-L). is offset by a stagger distance DS parallel to the first and second lateral trenches (e.g., horizontal shield-connection trenches 105-1 and 105-2). Staggering the active trench sections eliminates the need to process large (4-way) trench intersections.

In an exemplary embodiment, a horizontal trench (e.g., a shield-connecting trench 105) is used to intercept and traverse (i.e., traverse) trench 101 and mesa 102 to create an area for making a shield poly contact. )) may comprise a number of short-length, discontinuous trench segments, each traversing only a few trenches 101 and mesa 102 (e.g., 2 to 5 trenches 101 ). Additionally, these short length horizontal trench segments may traverse a small number of trenches 101 at different locations within the device layout.

FIG. 8 shows an example shielded gate trench MOSFET device 800 in which a short length of horizontal trench segment intersects perpendicularly with a few active trenches and traverses them to create a side area for making a shielding poly contact.

Like devices 600 and 700, device 800 may include an active trench 101 and mesa 102 extending in the y direction between two gate feeds. The two gate feeds are two gate feeds of gate metal (e.g., gate metal 710-1 and gate metal 710-2) connected to a gate electrode contact (e.g., contact 702) in the end region of active trench 101. It is formed by two sheets or strips.

The first short length shield-connected trench 105-3 is adjacent to trenches 101-1, 101-2 and 101-c (and mesas 102-1 and 102-2) at approximately position Y1 on the y-axis. )) extends laterally (e.g., in the x direction). A second short length of shield-connected trench 105-4 is adjacent to trenches 101-c, 101-3 and 101-4 (and mesas 102-3 and 102-4) at approximately position Y2 on the y-axis. )) extends laterally (e.g., in the x direction).

As shown in Figure 8, the short length shield-connected trench 105-3 connects each longitudinal trench 101-1 and 101-2 and each mesa 102-1 and 102-2 to 2 sections, e.g., an upper section in an upper region (e.g., region 12U) above shield-connected trench 105-3 in the y direction, and below shield-connected trench 105-3 in the y direction. effectively divides into a lower region (e.g., with a lower section in region 12L). The short length shield-connected trench 105-4 divides each longitudinal trench 101-3 and 101-4 and each mesa 102-3 and 102-4 into two sections (e.g., y an upper section in the upper region (e.g., region 14U) above the shield-connected trench 105-4 in the direction, and a lower region (e.g., region (14U)) below the shield-connected trench 105-4 in the y direction. 14L)), with the subsection at 14L)).

The short length of the shield-connecting trenches 105-3 and 105-4, due to their limited length or area, allows for a limited number of insulator-lined conductive-plugs 116 to make shielding poly contacts in the device 800. ) can only be accepted. For example, arrays 116C and 116D, each comprising two insulator-lined conductive-plugs 116, may be placed in short length shield-connection trenches 105-3 and 105-4, respectively. You can. However, the variety of positions in which the short length shield connection trenches 105-3 and 105-4 can be used (e.g. positions Y1 and Y2) and consequently insulator-lined conductive-plugs to create shielded poly contacts. The diversity of positions of (116) can result in device design flexibility and processing robustness.

In an example implementation, the MOSFET device includes a set of longitudinal trenches and longitudinal mesas extending longitudinally from a gate feed across the semiconductor substrate. The device includes a first lateral trench that perpendicularly intersects at least one of the set of longitudinal trenches and longitudinal mesas at a first distance from the gate feed, the first lateral trench being in fluid communication with the intersected at least one of the set of longitudinal trenches. 1 lateral trench, and a second lateral trench that perpendicularly intersects at least one of the set of longitudinal trenches and longitudinal mesas in the semiconductor substrate at a second distance from the gate feed, wherein at least one of the set of longitudinal trenches intersects and a second lateral trench in fluid communication with.

In a MOSFET device, the shielding poly layer is disposed in a longitudinal trench and a set of first and second lateral trenches. An inter-poly dielectric layer (IPD) and a gate poly layer are disposed over the shielding poly layer in a set of longitudinal and lateral trenches.

Additionally, in the MOSFET device, a first electrical contact to the shielding poly layer is made by a first insulator-lined conductive-plug passing through the gate poly layer and an inter-poly dielectric layer disposed in the first lateral trench; A second electrical contact to the shielding poly layer is made by a second insulator-lined conductive-plug passing through the gate poly layer and the inter-poly dielectric layer disposed in the second lateral trench.

In a MOSFET device, a gate poly disposed in at least one of the set of longitudinal trenches crossed by the first lateral trench includes a first inter-poly dielectric layer disposed in the first lateral trench and a first poly dielectric layer passing through the gate poly layer. It forms a continuous gate electrode of the device, uninterrupted by electrical contact to the shielding poly layer made by the insulator-lined conductive-plug. Additionally, the gate poly disposed in at least one of the set of longitudinal trenches intersected by the second lateral trench comprises an inter-poly dielectric layer disposed in the second lateral trench and a first insulator passing through the gate poly layer - It forms a continuous gate electrode of the device, uninterrupted by electrical contact to the shielding poly layer made by the lined conductive-plug.

In some example implementations of the MOSFET device, at least one of the set of longitudinal trenches crossed at a first distance by the first lateral trench includes at least one length crossed at a second distance by the second lateral trench. It is a set of longitudinal trenches that are different from directional trenches.

In some example implementations of the MOSFET device, at least one of the set of longitudinal trenches crossed at a first distance by the first lateral trench is a set of longitudinal trenches crossed at a second distance by the second lateral trench. Same as one of the sets.

In some example implementations of the MOSFET device, at least one of the set of longitudinal trenches crossed at a first distance by a first lateral trench and crossed at a second distance by a second lateral trench comprises a first lateral trench It is divided into a first section longitudinal trench on the side of the section, a mid-section longitudinal trench between the first and second lateral trenches, and a third section longitudinal trench on the side of the second lateral trench. In some example implementations of the device, the middle section longitudinal trench is offset relative to the first and second section longitudinal trenches by a staggered distance parallel to the first and second lateral trenches.

9 shows an example method 900 for reducing shield electrode resistance in a shielded gate trench MOSFET device.

Method 900 includes defining 910 a plurality of trenches of a first type in a semiconductor substrate. The plurality of trenches of the first type extend longitudinally (eg, from the gate feed region). Method 900 further includes defining 920 a second type of trench that extends laterally and intersects a plurality of trenches of the first type. The trenches of the second type are in fluid communication with each of the plurality of trenches of the first type crossed. Method 900 includes disposing 930 a shielding poly layer in a plurality of trenches of the first type and a plurality of trenches of a second type, comprising placing a poly-layer over the shielding poly layer in the plurality of trenches of the first type and the trenches of the second type. Disposing (940) an inter-dielectric layer (IPL) and a gate poly layer, and forming electrical contact to the shielding poly layer through an opening in the inter-poly inter-dielectric layer and gate poly layer disposed in the second type of trench. It further includes step 950.

In method 900, forming electrical contact to the shielding poly layer through the opening includes lining the opening with an insulator (e.g., an oxide) and inserting a metal (e.g., tungsten), metal alloy, metal silicide, or conductive material into the opening. and placing one of the polysilicon.

The method includes defining a plurality of trenches of a first type in a semiconductor substrate, wherein the plurality of trenches of the first type extend longitudinally; defining a second type of trench that extends laterally and intersects a plurality of trenches of the first type, wherein the second type of trench is in fluid communication with each of the intersected plurality of trenches of the first type; disposing a shielding poly layer in the plurality of trenches of the first type and the plurality of trenches of the second type; Disposing an inter-poly dielectric layer (IPL) and a gate poly layer over the shielding poly layer in the plurality of trenches of the first type and the trench of the second type; and forming electrical contact to the shielding poly layer through an opening in the gate poly layer and the inter-poly dielectric layer disposed in the second type of trench.

In the method described above, forming electrical contact to the shielding poly layer through the opening includes lining the opening with an insulator.

In the above-described method, forming electrical contact to the shielding poly layer through the opening includes disposing one of a metal, metal alloy, metal silicide, or conductive polysilicon in the opening.

In the method described above, forming electrical contact to the shielding poly layer through the opening includes disposing tungsten in the opening.

Certain structural and functional details disclosed herein are representative only for purposes of describing exemplary embodiments. However, the exemplary embodiments may be implemented in many alternative forms and should not be construed as limited to the embodiments set forth herein.

It will be understood that the specific number and geometric size and distribution of electrical contacts within the shield-connected trenches are not limited to those shown in the drawings herein.

For example, representative embodiments illustrated in the figures herein may include a specific number, geometric size, and arrangement of electrical contacts (e.g., by insulator-lined conductive-plug 116) in a shield-connected trench. You can. Representative embodiments illustrated in the figures include, for example, one electrical contact in the shield-connection trench per mesa or every two mesas, electrical contacts having a width similar to the width of one mesa or the width of two mesas, and generally It shows the mesa and geometrically aligned electrical contacts. Other embodiments within the scope of the present disclosure need not be limited to the representative examples shown in the drawings herein. For example, other embodiments may be aligned with a mesa-to-mesa trench, partially aligned with a mesa and an inter-mesa trench, or randomly positioned within a shield-connected trench regardless of alignment with a mesa or an inter-mesa trench. It may include electrical contact to be determined. For example, other embodiments may include electrical contacts of any width, not necessarily an integer multiple or integer fraction of the mesa width (or inter-mesa trench width). Similarly, other embodiments may include a number of contacts in the shield-connected trench, for example, not an integer multiple or integer fraction of the number of mesas (or inter-mesa trenches).

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some embodiments utilize various types of semiconductor processing techniques associated with semiconductor substrates, including, but not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc. It can be implemented using

The terminology used herein is intended to describe specific implementations only and is not intended to limit the implementations. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly dictates otherwise. As used herein, the terms “comprises,” “comprising,” “includes,” and/or “including” refer to a referenced feature, step, It will be further understood that specifying the presence of an operation, element and/or component does not exclude the presence or addition of one or more other features, steps, operations, elements, components and/or groups thereof.

When an element, such as a layer, region, or substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it is either directly on, connected to, or coupled to another element. , it will also be understood that more than one intervening element may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, no intervening elements or layers are present. The terms 'directly on,' 'directly connected to,' or 'directly coupled to' may not be used throughout the detailed description, but may be used throughout the detailed description. Elements shown as joined may be referred to as such. The claims of this application may be amended to recite exemplary relationships described in the specification or shown in the drawings.

As used herein, the singular forms include the plural forms, unless the context clearly dictates a particular instance. Spatially relative terms (e.g. over, above, upper, under, beneath, below, lower, etc.) refer to the orientation shown in the drawing. In addition, it is intended to include different orientations of the device in use or operation. In some implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some implementations, the term 'proximate' may include 'laterally proximate to' or 'horizontally proximate to'.

Exemplary implementations of the inventive concepts are described herein with reference to cross-sectional examples that are schematic illustrations of idealized implementations (and intermediate structures) of the exemplary implementations. As such, variations from the exemplary shape may be expected, for example, as a result of manufacturing techniques and/or tolerances. Accordingly, exemplary implementations of the inventive concepts should not be construed as limited to the regions of specific shapes illustrated herein, but should be construed to include variations in shape resulting, for example, from manufacturing. Accordingly, the areas illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of areas of the device and are not intended to limit the scope of the example implementations.

It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Accordingly, a “first” element may be referred to as a “second” element without departing from the teachings of this embodiment.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the inventive concept pertains. Terms as defined in commonly used dictionaries shall be construed to have meanings consistent with their meanings in the context of the relevant art and/or this specification, and, unless expressly defined herein, shall not be idealized or overly formal. It will be further understood that this will not be interpreted as meaning.

Although certain features of the described embodiments have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. Accordingly, it is to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments. It should be understood that this is presented only as an example and not a limitation, and that various changes in form and details may be made. Any portion of the devices and/or methods described herein may be combined in any combination, except for mutually exclusive combinations. Implementations described herein may include various combinations and/or sub-combinations of functions, components and/or features of the different implementations described.

Claims (23)

As devices (200, 300, 400, 500, 600, 700, 800),
A plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of a first direction type in a semiconductor substrate, The plurality of trenches of the first direction type include a plurality of trenches of the first direction type extending in the longitudinal direction;
a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) extending laterally and of the first direction type; Intersecting second direction type trenches (105, 105-1, 105-2, 105-3, 105-4), wherein the second direction type trenches (105, 105-1, 105-2, 105-3) , 105-4) is a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-) of the first direction type crossed. U) a second directional type of trench in fluid communication with each, the longitudinal direction being perpendicular to the transverse direction;
A plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first direction type and the second direction type a shielding poly layer 111 disposed in the trenches 105, 105-1, 105-2, 105-3, 105-4;
A plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first direction type and the second direction type An inter-poly dielectric layer (IPL) 112 disposed over the shielding poly layer 111 in the trenches 105, 105-1, 105-2, 105-3, 105-4 and a gate. poly layer 108; and
disposed within an opening in the gate poly layer (108) and the inter-poly dielectric layer (112) disposed in the second directional type trench (105, 105-1, 105-2, 105-3, 105-4). A device comprising an electrical contact (116) to the shielding poly layer (111). 2. The method of claim 1, wherein the electrical contacts to the inter-poly dielectric layer (112) and the shielding poly layer (111) disposed within openings (106, 16) in the gate poly layer (108) are insulator-lined ( device, which is an insulator-lined) conductive plug (116). 3. The device of claim 2, wherein the insulator-lined conductive-plug (116) is an oxide-lined conductive-plug. 3. The device of claim 2, wherein the conductive central portion (109) of the insulator-lined conductive-plug (116) comprises one of metal, metal alloy, metal silicide, or conductive polysilicon. 3. The device of claim 2, wherein the conductive central portion (109) of the insulator-lined conductive-plug (116) comprises tungsten. The method of claim 1, wherein a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first direction type The gate poly layer 108 disposed in the poly-inter-dielectric layer 112 disposed in the second direction type trenches 105, 105-1, 105-2, 105-3, and 105-4. and forming a continuous gate electrode of the device uninterrupted by electrical contact to the shielding poly layer disposed within an opening (106, 16) in the gate poly layer (108). As devices (200, 300, 400, 500, 600, 700, 800),
A plurality of longitudinal trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-) of a first direction type extending longitudinally parallel across the semiconductor substrate. M, 101-U) and longitudinal mesa (102, 102-1, 102-2, 102-3, 102-4);
A plurality of longitudinal trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101) extending in a transverse direction perpendicular to the longitudinal direction and of the first direction type -M, 101-U) and a second directional type of lateral trenches (105, 105-1, 105-2, 105-3, 105-4, wherein the lateral trenches 105, 105-1, 105-2, 105-3, 105-4 are a plurality of longitudinal trenches of the first direction type ( 101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and in fluid communication with the lateral trenches 105, 105-1, 105-2, 105-3, 105-4) are each of the plurality of longitudinal trenches and longitudinal mesas (102, 102-1, 102-2, 102-3, 102-4) as a first section longitudinal trench (101-U, 101-L, 101-M) and a first section mesa and a second section on the first side of the lateral trenches (105, 105-1, 105-2, 105-3, 105-4) a second trench opposite the first side of the longitudinal trenches 101-U, 101-L, 101-M and the lateral trenches 105, 105-1, 105-2, 105-3, 105-4; divided by a second section longitudinal mesa on the side, wherein the lateral trenches 105, 105-1, 105-2, 105-3, 105-4 are the first section longitudinal trench and the second section longitudinal trench. a lateral trench in fluid communication with each;
The plurality of longitudinal trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the lateral trenches (105, 105) a shielding poly layer 111 disposed at -1, 105-2, 105-3, 105-4);
The plurality of longitudinal trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the lateral trenches (105, 105) -1, 105-2, 105-3, 105-4) inter-poly dielectric layer (IPL) 112 and gate poly layer 108 disposed over the shielding poly layer; and
at least one layer extending through the inter-poly dielectric layer 112 and the gate poly layer 108 disposed in the lateral trenches 105, 105-1, 105-2, 105-3, 105-4. A device comprising electrical contact to the shielding poly layer (111) by an insulator-lined conductive-plug (116). 8. The method of claim 7, wherein the at least one insulator-lined conductive-plug (116), the first section longitudinal mesa, and the second section longitudinal mesa are located in the lateral trench (105, 105-1, 105-2). , 105-3, 105-4). 8. The method of claim 7, wherein the at least one insulator-lined conductive-plug (116), the first section longitudinal mesa, and the second section longitudinal trench (105, 105-1, 105-2) , 105-3, 105-4). The method of claim 7, wherein the plurality of longitudinal trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and Each of the mesas 102, 102-1, 102-2, 102-3, and 102-4 has a trench width and a mesa width, wherein the at least one insulator-lined conductive-plug 116 is equal to the mesa width. A device with a width equal to or smaller than that. The method of claim 7, wherein the plurality of longitudinal trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and mesa ( 102, 102-1, 102-2, 102-3, 102-4) each have a trench width and a mesa width, wherein the at least one insulator-lined conductive-plug 116 has a width greater than the mesa width. Having a device. 12. The device of claim 11, wherein the at least one insulator-lined conductive-plug (116) has a width approximately equal to the sum of two mesa widths and a trench width. 8. The method of claim 7, wherein the at least one insulator-lined conductive-plug (116) comprises a plurality of insulator-lined conductive-plugs disposed in the lateral trench, The number is the number of longitudinal trenches in the plurality of longitudinal trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) Approximately the same device. 8. The method of claim 7, wherein the at least one insulator-lined conductive-plug (116) comprises a plurality of insulators disposed in the lateral trench (105, 105-1, 105-2, 105-3, 105-4). - comprising lined conductive-plugs, wherein the number of insulator-lined conductive-plugs is in the plurality of longitudinal trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, device, which is approximately half the number of longitudinal trenches in 101-L, 101-M, 101-U). 8. The method of claim 7, wherein the inter-poly dielectric layer (112) disposed in the lateral trench (105, 105-1, 105-2, 105-3, 105-4) and in the gate poly layer (108) The device, wherein the at least one insulator-lined conductive-plug (116) is disposed in the space between the first section mesa and the second section mesa. 8. The device of claim 7, wherein the at least one insulator-lined conductive-plug in the inter-poly dielectric layer (112) and the gate poly layer (108) is an oxide-lined opening (106, 16). 8. The method of claim 7, wherein the electrical contact to the shielding poly layer (111) through the at least one insulator-lined conductive-plug (116) comprises one of a metal, metal alloy, metal silicide, or conductive polysilicon. A device that does. 8. The device of claim 7, wherein the electrical contact to the shielding poly layer (111) through the at least one insulator-lined conductive-plug (116) comprises tungsten. 8. The method of claim 7, wherein the plurality of longitudinal trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) and the side The gate poly layer 108 disposed in the directional trenches 105, 105-1, 105-2, 105-3, 105-4 is the inter-poly dielectric layer 112 disposed in the lateral trench and the forming a continuous gate electrode of the device uninterrupted by electrical contact to the shielding poly layer (111) by the at least one insulator-lined conductive-plug (116) through a gate poly layer (108). , device. As a method,
A step of defining a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of a first type in a semiconductor substrate. , the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type extend in the longitudinal direction. , step;
extending laterally and intersecting a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type. A step of defining a second type of trench (105, 105-1, 105-2, 105-3, 105-4), wherein the second type of trench (105, 105-1, 105-2, 105- 3, 105-4) is a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-) of the first type crossed. U) in fluid communication with each;
A plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type and trenches of the second type placing a shielding poly layer (111) at (105, 105-1, 105-2, 105-3, 105-4);
A plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type and trenches of the second type Disposing an inter-poly dielectric layer (IPD) 112 and a gate poly layer 108 over the shielding poly layer 111 in (105, 105-1, 105-2, 105-3, 105-4). ; and
an opening (106) in the inter-poly dielectric layer (112) and the gate poly layer (108) disposed in the second type of trench (105, 105-1, 105-2, 105-3, 105-4); Forming electrical contact to the shielding poly layer (111) via 16). 21. The method of claim 20, wherein forming electrical contact to the shielding poly layer (111) through the opening (106, 16) comprises lining the opening (106, 16) with an insulator. 21. The method of claim 20, wherein forming electrical contact to the shielding poly layer (111) through the opening (106, 16) comprises placing one of a metal, metal alloy, metal silicide, or conductive polysilicon in the opening. A method comprising the steps of: 21. The method of claim 20, wherein forming electrical contact to the shielding poly layer (111) through the opening (106, 16) comprises disposing tungsten in the opening.