DE60330965D1 - Verfahren zur Herstellung eines Halbleitersubstrats mit einer Schichtstruktur von aktivierten Dotierungsstoffen - Google Patents

Verfahren zur Herstellung eines Halbleitersubstrats mit einer Schichtstruktur von aktivierten Dotierungsstoffen

Info

Publication number
DE60330965D1
DE60330965D1 DE60330965T DE60330965T DE60330965D1 DE 60330965 D1 DE60330965 D1 DE 60330965D1 DE 60330965 T DE60330965 T DE 60330965T DE 60330965 T DE60330965 T DE 60330965T DE 60330965 D1 DE60330965 D1 DE 60330965D1
Authority
DE
Germany
Prior art keywords
dopant
region
layered structure
semiconductor substrate
thin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60330965T
Other languages
English (en)
Inventor
Radu C Surdeanu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
NXP BV
Original Assignee
Interuniversitair Microelektronica Centrum vzw IMEC
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC, NXP BV filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Application granted granted Critical
Publication of DE60330965D1 publication Critical patent/DE60330965D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/916—Autodoping control or utilization
DE60330965T 2003-10-17 2003-10-17 Verfahren zur Herstellung eines Halbleitersubstrats mit einer Schichtstruktur von aktivierten Dotierungsstoffen Expired - Lifetime DE60330965D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03447259A EP1524684B1 (de) 2003-10-17 2003-10-17 Verfahren zur Herstellung eines Halbleitersubstrats mit einer Schichtstruktur von aktivierten Dotierungsstoffen

Publications (1)

Publication Number Publication Date
DE60330965D1 true DE60330965D1 (de) 2010-03-04

Family

ID=34354656

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60330965T Expired - Lifetime DE60330965D1 (de) 2003-10-17 2003-10-17 Verfahren zur Herstellung eines Halbleitersubstrats mit einer Schichtstruktur von aktivierten Dotierungsstoffen

Country Status (7)

Country Link
US (2) US7214592B2 (de)
EP (1) EP1524684B1 (de)
JP (1) JP4750400B2 (de)
CN (1) CN100442444C (de)
AT (1) ATE455366T1 (de)
DE (1) DE60330965D1 (de)
TW (1) TWI256079B (de)

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US20060113591A1 (en) * 2004-11-30 2006-06-01 Chih-Hao Wan High performance CMOS devices and methods for making same
JP2006245338A (ja) * 2005-03-03 2006-09-14 Nec Electronics Corp 電界効果型トランジスタの製造方法
US7786003B1 (en) * 2005-05-25 2010-08-31 Advanced Micro Devices, Inc. Buried silicide local interconnect with sidewall spacers and method for making the same
US20070037326A1 (en) * 2005-08-09 2007-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow source/drain regions for CMOS transistors
US20070212861A1 (en) * 2006-03-07 2007-09-13 International Business Machines Corporation Laser surface annealing of antimony doped amorphized semiconductor region
KR101113533B1 (ko) * 2006-03-08 2012-02-29 어플라이드 머티어리얼스, 인코포레이티드 기판상에 형성되는 구조체의 열적 처리를 위한 장치 및 방법
US20070212859A1 (en) 2006-03-08 2007-09-13 Paul Carey Method of thermal processing structures formed on a substrate
JP2008041988A (ja) * 2006-08-08 2008-02-21 Hiroshima Univ ゲルマニウム（Ｇｅ）半導体デバイス製造方法。
KR100806791B1 (ko) * 2006-09-01 2008-02-27 동부일렉트로닉스 주식회사 두 단계 포켓 임플란트를 이용한 반도체 소자의 제조 방법
US7718513B2 (en) * 2007-04-13 2010-05-18 International Business Machines Corporation Forming silicided gate and contacts from polysilicon germanium and structure formed
US8198547B2 (en) 2009-07-23 2012-06-12 Lexmark International, Inc. Z-directed pass-through components for printed circuit boards
US8012843B2 (en) * 2009-08-07 2011-09-06 Varian Semiconductor Equipment Associates, Inc. Optimized halo or pocket cold implants
US8943684B2 (en) 2011-08-31 2015-02-03 Lexmark International, Inc. Continuous extrusion process for manufacturing a Z-directed component for a printed circuit board
US9009954B2 (en) 2011-08-31 2015-04-21 Lexmark International, Inc. Process for manufacturing a Z-directed component for a printed circuit board using a sacrificial constraining material
US9078374B2 (en) * 2011-08-31 2015-07-07 Lexmark International, Inc. Screening process for manufacturing a Z-directed component for a printed circuit board
CN107068753B (zh) * 2011-12-19 2020-09-04 英特尔公司 通过部分熔化升高的源极-漏极的晶体管的脉冲激光退火工艺

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US4659392A (en) * 1985-03-21 1987-04-21 Hughes Aircraft Company Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuits
JPH03131020A (ja) * 1989-10-16 1991-06-04 Sanyo Electric Co Ltd 半導体装置の製造方法
JPH0492477A (ja) * 1990-08-08 1992-03-25 Hitachi Ltd 可変容量ダイオードの製造方法
US5171700A (en) * 1991-04-01 1992-12-15 Sgs-Thomson Microelectronics, Inc. Field effect transistor structure and method
JPH07321313A (ja) * 1994-05-24 1995-12-08 Sanyo Electric Co Ltd 半導体デバイスの製造方法
KR0146525B1 (ko) * 1995-05-09 1998-11-02 김주용 반도체 소자의 트랜지스터 제조방법
KR100232206B1 (ko) * 1996-12-26 1999-12-01 김영환 반도체 소자의 제조방법
KR100260044B1 (ko) * 1997-11-25 2000-07-01 윤종용 고속/고성능 모스 트랜지스터 및 그 제조방법
US6521502B1 (en) * 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6891235B1 (en) * 2000-11-15 2005-05-10 International Business Machines Corporation FET with T-shaped gate
DE10058031B4 (de) * 2000-11-23 2007-11-22 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Bildung leicht dotierter Halogebiete und Erweiterungsgebiete in einem Halbleiterbauelement
US20020086502A1 (en) * 2000-12-29 2002-07-04 Liu Mark Y. Method of forming a doped region in a semiconductor material
JP3904936B2 (ja) * 2001-03-02 2007-04-11 富士通株式会社 半導体装置の製造方法
JP2003086798A (ja) * 2001-09-13 2003-03-20 Nec Corp 半導体装置およびその製造方法
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Also Published As

Publication number Publication date
JP2005129930A (ja) 2005-05-19
CN1645568A (zh) 2005-07-27
CN100442444C (zh) 2008-12-10
ATE455366T1 (de) 2010-01-15
JP4750400B2 (ja) 2011-08-17
TWI256079B (en) 2006-06-01
TW200515489A (en) 2005-05-01
US20050112831A1 (en) 2005-05-26
US7214592B2 (en) 2007-05-08
US20070267660A1 (en) 2007-11-22
EP1524684B1 (de) 2010-01-13
EP1524684A1 (de) 2005-04-20

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