TWI256079B - Method for providing a semiconductor substrate with a layer structure of activated dopants - Google Patents

Method for providing a semiconductor substrate with a layer structure of activated dopants

Info

Publication number
TWI256079B
TWI256079B TW093130103A TW93130103A TWI256079B TW I256079 B TWI256079 B TW I256079B TW 093130103 A TW093130103 A TW 093130103A TW 93130103 A TW93130103 A TW 93130103A TW I256079 B TWI256079 B TW I256079B
Authority
TW
Taiwan
Prior art keywords
dopant
region
semiconductor substrate
thin layer
providing
Prior art date
Application number
TW093130103A
Other languages
English (en)
Other versions
TW200515489A (en
Inventor
Radu Catalin Surdeanu
Original Assignee
Imec Inter Uni Micro Electr
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec Inter Uni Micro Electr, Koninkl Philips Electronics Nv filed Critical Imec Inter Uni Micro Electr
Publication of TW200515489A publication Critical patent/TW200515489A/zh
Application granted granted Critical
Publication of TWI256079B publication Critical patent/TWI256079B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/914Doping
    • Y10S438/916Autodoping control or utilization

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
TW093130103A 2003-10-17 2004-10-05 Method for providing a semiconductor substrate with a layer structure of activated dopants TWI256079B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03447259A EP1524684B1 (en) 2003-10-17 2003-10-17 Method for providing a semiconductor substrate with a layer structure of activated dopants

Publications (2)

Publication Number Publication Date
TW200515489A TW200515489A (en) 2005-05-01
TWI256079B true TWI256079B (en) 2006-06-01

Family

ID=34354656

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093130103A TWI256079B (en) 2003-10-17 2004-10-05 Method for providing a semiconductor substrate with a layer structure of activated dopants

Country Status (7)

Country Link
US (2) US7214592B2 (zh)
EP (1) EP1524684B1 (zh)
JP (1) JP4750400B2 (zh)
CN (1) CN100442444C (zh)
AT (1) ATE455366T1 (zh)
DE (1) DE60330965D1 (zh)
TW (1) TWI256079B (zh)

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JP2006245338A (ja) * 2005-03-03 2006-09-14 Nec Electronics Corp 電界効果型トランジスタの製造方法
US7786003B1 (en) 2005-05-25 2010-08-31 Advanced Micro Devices, Inc. Buried silicide local interconnect with sidewall spacers and method for making the same
US20070037326A1 (en) * 2005-08-09 2007-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow source/drain regions for CMOS transistors
US20070212861A1 (en) * 2006-03-07 2007-09-13 International Business Machines Corporation Laser surface annealing of antimony doped amorphized semiconductor region
WO2007103643A2 (en) * 2006-03-08 2007-09-13 Applied Materials, Inc. Method and apparatus for thermal processing structures formed on a substrate
US7569463B2 (en) * 2006-03-08 2009-08-04 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
JP2008041988A (ja) * 2006-08-08 2008-02-21 Hiroshima Univ ゲルマニウム(Ge)半導体デバイス製造方法。
KR100806791B1 (ko) * 2006-09-01 2008-02-27 동부일렉트로닉스 주식회사 두 단계 포켓 임플란트를 이용한 반도체 소자의 제조 방법
US7718513B2 (en) * 2007-04-13 2010-05-18 International Business Machines Corporation Forming silicided gate and contacts from polysilicon germanium and structure formed
US8198547B2 (en) 2009-07-23 2012-06-12 Lexmark International, Inc. Z-directed pass-through components for printed circuit boards
US8012843B2 (en) * 2009-08-07 2011-09-06 Varian Semiconductor Equipment Associates, Inc. Optimized halo or pocket cold implants
US9078374B2 (en) * 2011-08-31 2015-07-07 Lexmark International, Inc. Screening process for manufacturing a Z-directed component for a printed circuit board
US8943684B2 (en) 2011-08-31 2015-02-03 Lexmark International, Inc. Continuous extrusion process for manufacturing a Z-directed component for a printed circuit board
US9009954B2 (en) 2011-08-31 2015-04-21 Lexmark International, Inc. Process for manufacturing a Z-directed component for a printed circuit board using a sacrificial constraining material
CN107068753B (zh) * 2011-12-19 2020-09-04 英特尔公司 通过部分熔化升高的源极-漏极的晶体管的脉冲激光退火工艺

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Also Published As

Publication number Publication date
CN100442444C (zh) 2008-12-10
JP2005129930A (ja) 2005-05-19
EP1524684B1 (en) 2010-01-13
JP4750400B2 (ja) 2011-08-17
US7214592B2 (en) 2007-05-08
ATE455366T1 (de) 2010-01-15
DE60330965D1 (de) 2010-03-04
US20070267660A1 (en) 2007-11-22
US20050112831A1 (en) 2005-05-26
TW200515489A (en) 2005-05-01
CN1645568A (zh) 2005-07-27
EP1524684A1 (en) 2005-04-20

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