DE60324353D1 - Delaminationsverfahren von Materialschichten - Google Patents

Delaminationsverfahren von Materialschichten

Info

Publication number
DE60324353D1
DE60324353D1 DE60324353T DE60324353T DE60324353D1 DE 60324353 D1 DE60324353 D1 DE 60324353D1 DE 60324353 T DE60324353 T DE 60324353T DE 60324353 T DE60324353 T DE 60324353T DE 60324353 D1 DE60324353 D1 DE 60324353D1
Authority
DE
Germany
Prior art keywords
temperature
phase
treatment
layers
degrees
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60324353T
Other languages
English (en)
Inventor
Walter Schwarzenbach
Christophe Maleville
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Application granted granted Critical
Publication of DE60324353D1 publication Critical patent/DE60324353D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Processing And Handling Of Plastics And Other Materials For Molding In General (AREA)
  • Heat Treatment Of Strip Materials And Filament Materials (AREA)
  • Glass Compositions (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Laminated Bodies (AREA)
DE60324353T 2002-05-02 2003-04-30 Delaminationsverfahren von Materialschichten Expired - Lifetime DE60324353D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0205500A FR2839385B1 (fr) 2002-05-02 2002-05-02 Procede de decollement de couches de materiau

Publications (1)

Publication Number Publication Date
DE60324353D1 true DE60324353D1 (de) 2008-12-11

Family

ID=28800114

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60324353T Expired - Lifetime DE60324353D1 (de) 2002-05-02 2003-04-30 Delaminationsverfahren von Materialschichten

Country Status (10)

Country Link
US (2) US6828216B2 (de)
EP (1) EP1359615B1 (de)
JP (1) JP4688408B2 (de)
KR (1) KR100796833B1 (de)
CN (1) CN1323426C (de)
AT (1) ATE412973T1 (de)
DE (1) DE60324353D1 (de)
FR (1) FR2839385B1 (de)
SG (1) SG127693A1 (de)
TW (1) TWI270931B (de)

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US6912330B2 (en) * 2001-05-17 2005-06-28 Sioptical Inc. Integrated optical/electronic circuits and associated methods of simultaneous generation thereof
FR2839385B1 (fr) * 2002-05-02 2004-07-23 Soitec Silicon On Insulator Procede de decollement de couches de materiau
FR2874455B1 (fr) * 2004-08-19 2008-02-08 Soitec Silicon On Insulator Traitement thermique avant collage de deux plaquettes
EP1429381B1 (de) * 2002-12-10 2011-07-06 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Herstellung eines Verbundmaterials
FR2858715B1 (fr) * 2003-08-04 2005-12-30 Soitec Silicon On Insulator Procede de detachement de couche de semiconducteur
US7510948B2 (en) 2003-09-05 2009-03-31 Sumco Corporation Method for producing SOI wafer
FR2867310B1 (fr) 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
FR2867307B1 (fr) 2004-03-05 2006-05-26 Soitec Silicon On Insulator Traitement thermique apres detachement smart-cut
US7282449B2 (en) 2004-03-05 2007-10-16 S.O.I.Tec Silicon On Insulator Technologies Thermal treatment of a semiconductor layer
JP2006203087A (ja) * 2005-01-24 2006-08-03 Sumco Corp 薄膜ｓｏｉウェーハのマイクロラフネス評価方法
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
JP2007173354A (ja) 2005-12-20 2007-07-05 Shin Etsu Chem Co Ltd Ｓｏｉ基板およびｓｏｉ基板の製造方法
KR100738460B1 (ko) 2005-12-23 2007-07-11 주식회사 실트론 나노 에스오아이 웨이퍼의 제조방법
US8835802B2 (en) * 2006-01-24 2014-09-16 Stephen C. Baer Cleaving wafers from silicon crystals
US7863157B2 (en) 2006-03-17 2011-01-04 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
WO2007118121A2 (en) 2006-04-05 2007-10-18 Silicon Genesis Corporation Method and structure for fabricating solar cells using a layer transfer process
FR2899594A1 (fr) 2006-04-10 2007-10-12 Commissariat Energie Atomique Procede d'assemblage de substrats avec traitements thermiques a basses temperatures
JP5028845B2 (ja) 2006-04-14 2012-09-19 株式会社Ｓｕｍｃｏ 貼り合わせウェーハ及びその製造方法
CN101432849B (zh) * 2006-04-27 2011-03-16 信越半导体股份有限公司 Soi晶片的制造方法
US8153513B2 (en) 2006-07-25 2012-04-10 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process
US8293619B2 (en) * 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US9362439B2 (en) * 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
FR2905801B1 (fr) * 2006-09-12 2008-12-05 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
US8124499B2 (en) * 2006-11-06 2012-02-28 Silicon Genesis Corporation Method and structure for thick layer transfer using a linear accelerator
US20080128641A1 (en) * 2006-11-08 2008-06-05 Silicon Genesis Corporation Apparatus and method for introducing particles using a radio frequency quadrupole linear accelerator for semiconductor materials
US20080188011A1 (en) * 2007-01-26 2008-08-07 Silicon Genesis Corporation Apparatus and method of temperature conrol during cleaving processes of thick film materials
FR2914496B1 (fr) * 2007-03-29 2009-10-02 Soitec Silicon On Insulator Amelioration de la defectivite post decollement d'une couche mince par modification de son recuit de decollement.
FR2914495B1 (fr) * 2007-03-29 2009-10-02 Soitec Silicon On Insulator Amelioration de la qualite d'une couche mince par recuit thermique haute temperature.
FR2919960B1 (fr) 2007-08-08 2010-05-21 Soitec Silicon On Insulator Procede et installation pour la fracture d'un substrat composite selon un plan de fragilisation
JP2009283582A (ja) * 2008-05-21 2009-12-03 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法及び貼り合わせウェーハ
JP5263509B2 (ja) * 2008-09-19 2013-08-14 信越半導体株式会社 貼り合わせウェーハの製造方法
JP5493343B2 (ja) * 2008-12-04 2014-05-14 信越半導体株式会社 貼り合わせウェーハの製造方法
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
FR2954585B1 (fr) * 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
FR2968121B1 (fr) 2010-11-30 2012-12-21 Soitec Silicon On Insulator Procede de transfert d'une couche a haute temperature
CN103370800A (zh) * 2010-12-29 2013-10-23 Gtat公司 用于形成薄层板的方法和设备
JP6056516B2 (ja) * 2013-02-01 2017-01-11 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
JP6136786B2 (ja) * 2013-09-05 2017-05-31 信越半導体株式会社 貼り合わせウェーハの製造方法
CN106711027B (zh) * 2017-02-13 2021-01-05 中国科学院上海微系统与信息技术研究所 晶圆键合方法及异质衬底制备方法
FR3108440A1 (fr) * 2020-03-23 2021-09-24 Soitec Procédé de préparation d’une couche mince
US11377758B2 (en) 2020-11-23 2022-07-05 Stephen C. Baer Cleaving thin wafers from crystals
FR3132384B1 (fr) * 2022-01-31 2024-01-12 Soitec Silicon On Insulator Procede de transfert d’une couche mince sur un substrat support

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
DE69619251T2 (de) 1995-09-04 2002-10-02 Nakasu Denki K.K., Seki Teil und instrument um konduktivität bei einer elektrischen verbindung zu erreichen
JPH10303139A (ja) * 1997-04-28 1998-11-13 Denso Corp 半導体基板の製造方法
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
FR2767416B1 (fr) * 1997-08-12 1999-10-01 Commissariat Energie Atomique Procede de fabrication d'un film mince de materiau solide
WO1999030370A1 (fr) * 1997-12-09 1999-06-17 Seiko Epson Corporation Dispositif a semi-conducteur et procede de fabrication, dispositif electro-optique et procede de fabrication, et appareil electronique y ayant recours
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
US6540827B1 (en) * 1998-02-17 2003-04-01 Trustees Of Columbia University In The City Of New York Slicing of single-crystal films using ion implantation
JPH11307747A (ja) * 1998-04-17 1999-11-05 Nec Corp Ｓｏｉ基板およびその製造方法
JPH11307472A (ja) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd 水素イオン剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP3911901B2 (ja) * 1999-04-09 2007-05-09 信越半導体株式会社 Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法
US6287941B1 (en) * 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
US6881644B2 (en) * 1999-04-21 2005-04-19 Silicon Genesis Corporation Smoothing method for cleaved films made using a release layer
US6368938B1 (en) * 1999-10-05 2002-04-09 Silicon Wafer Technologies, Inc. Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate
WO2001028000A1 (fr) * 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Procede de fabrication d'une tranche de soi, et tranche de soi
KR100393208B1 (ko) * 2001-01-15 2003-07-31 삼성전자주식회사 도핑된 다결정 실리콘-저매니움막을 이용한 반도체 소자및 그 제조방법
FR2821697B1 (fr) * 2001-03-02 2004-06-25 Commissariat Energie Atomique Procede de fabrication de couches minces sur un support specifique et une application
FR2839385B1 (fr) * 2002-05-02 2004-07-23 Soitec Silicon On Insulator Procede de decollement de couches de materiau
US6812116B2 (en) * 2002-12-13 2004-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance

Also Published As

Publication number Publication date
TW200402770A (en) 2004-02-16
EP1359615A1 (de) 2003-11-05
US6828216B2 (en) 2004-12-07
JP4688408B2 (ja) 2011-05-25
KR100796833B1 (ko) 2008-01-22
CN1479353A (zh) 2004-03-03
US20030216008A1 (en) 2003-11-20
US20050101104A1 (en) 2005-05-12
JP2003347526A (ja) 2003-12-05
TWI270931B (en) 2007-01-11
ATE412973T1 (de) 2008-11-15
EP1359615B1 (de) 2008-10-29
US7300856B2 (en) 2007-11-27
FR2839385A1 (fr) 2003-11-07
SG127693A1 (en) 2006-12-29
FR2839385B1 (fr) 2004-07-23
KR20030086436A (ko) 2003-11-10
CN1323426C (zh) 2007-06-27

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