DE602005004553T2 - Flash-speichereinheit und verfahren zur programmierung einer flash-speichereinheit - Google Patents
Flash-speichereinheit und verfahren zur programmierung einer flash-speichereinheit Download PDFInfo
- Publication number
- DE602005004553T2 DE602005004553T2 DE602005004553T DE602005004553T DE602005004553T2 DE 602005004553 T2 DE602005004553 T2 DE 602005004553T2 DE 602005004553 T DE602005004553 T DE 602005004553T DE 602005004553 T DE602005004553 T DE 602005004553T DE 602005004553 T2 DE602005004553 T2 DE 602005004553T2
- Authority
- DE
- Germany
- Prior art keywords
- voltage
- source
- memory device
- programming
- pass transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 26
- 238000007667 floating Methods 0.000 claims description 16
- 238000005513 bias potential Methods 0.000 claims description 12
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 230000004044 response Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 240000005020 Acaciella glauca Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000036316 preload Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Landscapes
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US909693 | 2004-08-02 | ||
| US10/909,693 US7042767B2 (en) | 2004-08-02 | 2004-08-02 | Flash memory unit and method of programming a flash memory device |
| PCT/US2005/014979 WO2006022908A1 (en) | 2004-08-02 | 2005-04-29 | Flash memory unit and method of programming a flash memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE602005004553D1 DE602005004553D1 (de) | 2008-03-13 |
| DE602005004553T2 true DE602005004553T2 (de) | 2009-01-29 |
Family
ID=34968955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602005004553T Active DE602005004553T2 (de) | 2004-08-02 | 2005-04-29 | Flash-speichereinheit und verfahren zur programmierung einer flash-speichereinheit |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7042767B2 (ja) |
| EP (1) | EP1774530B1 (ja) |
| JP (1) | JP2008508662A (ja) |
| KR (1) | KR100928737B1 (ja) |
| CN (1) | CN1993767A (ja) |
| DE (1) | DE602005004553T2 (ja) |
| TW (1) | TWI373047B (ja) |
| WO (1) | WO2006022908A1 (ja) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8587049B2 (en) * | 2006-07-17 | 2013-11-19 | Spansion, Llc | Memory cell system with charge trap |
| US7586787B2 (en) * | 2007-09-20 | 2009-09-08 | Kilopass Technology Inc. | Reducing bit line leakage current in non-volatile memories |
| US7764547B2 (en) * | 2007-12-20 | 2010-07-27 | Sandisk Corporation | Regulation of source potential to combat cell source IR drop |
| US8274829B2 (en) * | 2008-06-09 | 2012-09-25 | Aplus Flash Technology, Inc. | Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS |
| US8295087B2 (en) * | 2008-06-16 | 2012-10-23 | Aplus Flash Technology, Inc. | Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS |
| US8289775B2 (en) * | 2008-06-20 | 2012-10-16 | Aplus Flash Technology, Inc. | Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array |
| CN104769661B (zh) | 2012-11-05 | 2017-07-18 | 佛罗里达大学研究基金会有限公司 | 显示器中的亮度补偿 |
| CN112863580A (zh) * | 2021-01-22 | 2021-05-28 | 珠海创飞芯科技有限公司 | 一种存储器的编程方法及存储器 |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5204835A (en) * | 1990-06-13 | 1993-04-20 | Waferscale Integration Inc. | Eprom virtual ground array |
| US5346842A (en) * | 1992-02-04 | 1994-09-13 | National Semiconductor Corporation | Method of making alternate metal/source virtual ground flash EPROM cell array |
| JP2917722B2 (ja) * | 1993-01-07 | 1999-07-12 | 日本電気株式会社 | 電気的書込消去可能な不揮発性半導体記憶装置 |
| US5717634A (en) * | 1995-07-19 | 1998-02-10 | Texas Instruments Incorporated | Programmable and convertible non-volatile memory array |
| US6009017A (en) * | 1998-03-13 | 1999-12-28 | Macronix International Co., Ltd. | Floating gate memory with substrate band-to-band tunneling induced hot electron injection |
| US5875130A (en) * | 1998-05-27 | 1999-02-23 | Advanced Micro Devices | Method for programming flash electrically erasable programmable read-only memory |
| US5901090A (en) * | 1998-05-27 | 1999-05-04 | Advanced Micro Devices | Method for erasing flash electrically erasable programmable read-only memory (EEPROM) |
| US6309926B1 (en) * | 1998-12-04 | 2001-10-30 | Advanced Micro Devices | Thin resist with nitride hard mask for gate etch application |
| US6046932A (en) * | 1999-08-13 | 2000-04-04 | Advanced Micro Devices, Inc. | Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM |
| US6275415B1 (en) * | 1999-10-12 | 2001-08-14 | Advanced Micro Devices, Inc. | Multiple byte channel hot electron programming using ramped gate and source bias voltage |
| JP2001195890A (ja) * | 2000-01-12 | 2001-07-19 | Sharp Corp | 不揮発性半導体メモリ装置の書込み方式および書込み回路 |
| US6215702B1 (en) * | 2000-02-16 | 2001-04-10 | Advanced Micro Devices, Inc. | Method of maintaining constant erasing speeds for non-volatile memory cells |
| US6356482B1 (en) * | 2000-02-24 | 2002-03-12 | Advanced Micro Devices, Inc. | Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure |
| US6295228B1 (en) * | 2000-02-28 | 2001-09-25 | Advanced Micro Devices, Inc. | System for programming memory cells |
| US6246611B1 (en) * | 2000-02-28 | 2001-06-12 | Advanced Micro Devices, Inc. | System for erasing a memory cell |
| US6331951B1 (en) * | 2000-11-21 | 2001-12-18 | Advanced Micro Devices, Inc. | Method and system for embedded chip erase verification |
| US6344994B1 (en) * | 2001-01-31 | 2002-02-05 | Advanced Micro Devices | Data retention characteristics as a result of high temperature bake |
| US6400624B1 (en) * | 2001-02-26 | 2002-06-04 | Advanced Micro Devices, Inc. | Configure registers and loads to tailor a multi-level cell flash design |
| US6307784B1 (en) * | 2001-02-28 | 2001-10-23 | Advanced Micro Devices | Negative gate erase |
| US6456533B1 (en) * | 2001-02-28 | 2002-09-24 | Advanced Micro Devices, Inc. | Higher program VT and faster programming rates based on improved erase methods |
| US6442074B1 (en) * | 2001-02-28 | 2002-08-27 | Advanced Micro Devices, Inc. | Tailored erase method using higher program VT and higher negative gate erase |
| US6510085B1 (en) * | 2001-05-18 | 2003-01-21 | Advanced Micro Devices, Inc. | Method of channel hot electron programming for short channel NOR flash arrays |
| US6522585B2 (en) * | 2001-05-25 | 2003-02-18 | Sandisk Corporation | Dual-cell soft programming for virtual-ground memory arrays |
| US6370061B1 (en) * | 2001-06-19 | 2002-04-09 | Advanced Micro Devices, Inc. | Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells |
| JP2003123493A (ja) * | 2001-10-12 | 2003-04-25 | Fujitsu Ltd | ソース電位を制御してプログラム動作を最適化した不揮発性メモリ |
-
2004
- 2004-08-02 US US10/909,693 patent/US7042767B2/en active Active
-
2005
- 2005-04-29 DE DE602005004553T patent/DE602005004553T2/de active Active
- 2005-04-29 WO PCT/US2005/014979 patent/WO2006022908A1/en active IP Right Grant
- 2005-04-29 JP JP2007524789A patent/JP2008508662A/ja active Pending
- 2005-04-29 EP EP05746549A patent/EP1774530B1/en active Active
- 2005-04-29 KR KR1020077003028A patent/KR100928737B1/ko not_active IP Right Cessation
- 2005-04-29 CN CNA2005800262535A patent/CN1993767A/zh active Pending
- 2005-07-29 TW TW094125726A patent/TWI373047B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| EP1774530B1 (en) | 2008-01-23 |
| US20060023511A1 (en) | 2006-02-02 |
| US7042767B2 (en) | 2006-05-09 |
| KR20070038547A (ko) | 2007-04-10 |
| TW200620295A (en) | 2006-06-16 |
| DE602005004553D1 (de) | 2008-03-13 |
| WO2006022908A1 (en) | 2006-03-02 |
| KR100928737B1 (ko) | 2009-11-27 |
| TWI373047B (en) | 2012-09-21 |
| CN1993767A (zh) | 2007-07-04 |
| EP1774530A1 (en) | 2007-04-18 |
| JP2008508662A (ja) | 2008-03-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |