DE60111348D1 - Verfahren zum Auslesen eines nichtflüchtigen Halbleiterspeichers und nichtflüchtiger Halbleiterspeicher - Google Patents

Verfahren zum Auslesen eines nichtflüchtigen Halbleiterspeichers und nichtflüchtiger Halbleiterspeicher

Info

Publication number
DE60111348D1
DE60111348D1 DE60111348T DE60111348T DE60111348D1 DE 60111348 D1 DE60111348 D1 DE 60111348D1 DE 60111348 T DE60111348 T DE 60111348T DE 60111348 T DE60111348 T DE 60111348T DE 60111348 D1 DE60111348 D1 DE 60111348D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
nonvolatile semiconductor
reading out
nonvolatile
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60111348T
Other languages
English (en)
Other versions
DE60111348T2 (de
Inventor
Mitsuteru Iijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60111348D1 publication Critical patent/DE60111348D1/de
Publication of DE60111348T2 publication Critical patent/DE60111348T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE60111348T 2001-02-26 2001-12-31 Verfahren zum Auslesen eines nichtflüchtigen Halbleiterspeichers und nichtflüchtiger Halbleiterspeicher Expired - Lifetime DE60111348T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001050124 2001-02-26
JP2001050124A JP4467815B2 (ja) 2001-02-26 2001-02-26 不揮発性半導体メモリの読み出し動作方法および不揮発性半導体メモリ

Publications (2)

Publication Number Publication Date
DE60111348D1 true DE60111348D1 (de) 2005-07-14
DE60111348T2 DE60111348T2 (de) 2005-11-10

Family

ID=18911137

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60111348T Expired - Lifetime DE60111348T2 (de) 2001-02-26 2001-12-31 Verfahren zum Auslesen eines nichtflüchtigen Halbleiterspeichers und nichtflüchtiger Halbleiterspeicher

Country Status (6)

Country Link
US (1) US6650568B2 (de)
EP (1) EP1235229B1 (de)
JP (1) JP4467815B2 (de)
KR (1) KR100688998B1 (de)
DE (1) DE60111348T2 (de)
TW (1) TW519753B (de)

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JP4156248B2 (ja) * 2002-02-18 2008-09-24 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6992932B2 (en) 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6963505B2 (en) 2002-10-29 2005-11-08 Aifun Semiconductors Ltd. Method circuit and system for determining a reference voltage
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
WO2005094178A2 (en) 2004-04-01 2005-10-13 Saifun Semiconductors Ltd. Method, circuit and systems for erasing one or more non-volatile memory cells
US7755938B2 (en) * 2004-04-19 2010-07-13 Saifun Semiconductors Ltd. Method for reading a memory array with neighbor effect cancellation
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
JP4410188B2 (ja) 2004-11-12 2010-02-03 株式会社東芝 半導体記憶装置のデータ書き込み方法
US7257025B2 (en) * 2004-12-09 2007-08-14 Saifun Semiconductors Ltd Method for reading non-volatile memory cells
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US7209406B2 (en) * 2005-05-19 2007-04-24 Macronix International Co., Ltd. Memory device with rapid word line switch
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
EP1746645A3 (de) 2005-07-18 2009-01-21 Saifun Semiconductors Ltd. Speicherzellenanordnung mit sub-minimalem Wortleitungsabstand und Verfahren zu deren Herstellung
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
JP2007087441A (ja) * 2005-09-20 2007-04-05 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置
US7345917B2 (en) * 2005-12-05 2008-03-18 Macronix International Co., Ltd. Non-volatile memory package and method of reading stored data from a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7471568B2 (en) * 2006-06-21 2008-12-30 Macronix International Co., Ltd. Multi-level cell memory structures with enlarged second bit operation window
US20070297244A1 (en) * 2006-06-21 2007-12-27 Macronix International Co., Ltd. Top Dielectric Structures in Memory Devices and Methods for Expanding a Second Bit Operation Window
US7675783B2 (en) * 2007-02-27 2010-03-09 Samsung Electronics Co., Ltd. Nonvolatile memory device and driving method thereof
KR101371522B1 (ko) * 2007-02-27 2014-03-12 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 구동 방법
US7843730B2 (en) * 2008-01-16 2010-11-30 Freescale Semiconductor, Inc. Non-volatile memory with reduced charge fluence
KR101378602B1 (ko) * 2008-05-13 2014-03-25 삼성전자주식회사 메모리 장치 및 메모리 프로그래밍 방법
KR101518199B1 (ko) 2008-05-23 2015-05-06 삼성전자주식회사 오류 정정 장치, 그 방법 및 상기 장치를 포함하는 메모리장치
JP5368266B2 (ja) * 2009-11-11 2013-12-18 ローム株式会社 半導体不揮発記憶回路
JP2012069192A (ja) * 2010-09-22 2012-04-05 Toshiba Corp メモリシステム
CN103366790A (zh) * 2012-03-30 2013-10-23 硅存储技术公司 用于读出放大器的可调整参考发生器

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JPS6342099A (ja) * 1986-08-06 1988-02-23 Fujitsu Ltd ３値レベルｒｏｍ
JP2904498B2 (ja) * 1989-03-06 1999-06-14 株式会社東芝 不揮発性半導体メモリ装置およびその製造方法
JPH06137726A (ja) * 1991-05-31 1994-05-20 Suzuki Motor Corp 自動車用空調装置の高低圧スイッチと溶栓の取付配置
JP3112182B2 (ja) * 1991-08-20 2000-11-27 日本テキサス・インスツルメンツ株式会社 多値リードオンリーメモリ装置
JP3179943B2 (ja) * 1993-07-12 2001-06-25 株式会社東芝 半導体記憶装置
US5526306A (en) * 1994-02-10 1996-06-11 Mega Chips Corporation Semiconductor memory device and method of fabricating the same
US5796149A (en) * 1994-09-09 1998-08-18 Nippon Steel Corporation Semiconductor memory using different concentration impurity diffused layers
JP2980012B2 (ja) * 1995-10-16 1999-11-22 日本電気株式会社 不揮発性半導体記憶装置
US5736771A (en) * 1996-02-07 1998-04-07 United Microelectronics Corporation Mask ROM cell structure with multi-level data selection by code
JPH1011979A (ja) * 1996-06-19 1998-01-16 Sony Corp 半導体不揮発性記憶装置
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US6137726A (en) * 1997-11-25 2000-10-24 Samsung Electronics Co., Ltd. Multi-level memory devices having memory cell referenced word line voltage generations
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JP5796149B1 (ja) * 2014-03-25 2015-10-21 三島光産株式会社 連続鋳造用鋳型

Also Published As

Publication number Publication date
TW519753B (en) 2003-02-01
KR20030009056A (ko) 2003-01-29
DE60111348T2 (de) 2005-11-10
JP2002251893A (ja) 2002-09-06
EP1235229A2 (de) 2002-08-28
EP1235229A3 (de) 2002-10-02
KR100688998B1 (ko) 2007-03-08
US6650568B2 (en) 2003-11-18
JP4467815B2 (ja) 2010-05-26
EP1235229B1 (de) 2005-06-08
US20020118570A1 (en) 2002-08-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE