DE60127635D1 - Speicher, Verfahren und Anordnung zum Schreiben und Lesen - Google Patents

Speicher, Verfahren und Anordnung zum Schreiben und Lesen

Info

Publication number
DE60127635D1
DE60127635D1 DE60127635T DE60127635T DE60127635D1 DE 60127635 D1 DE60127635 D1 DE 60127635D1 DE 60127635 T DE60127635 T DE 60127635T DE 60127635 T DE60127635 T DE 60127635T DE 60127635 D1 DE60127635 D1 DE 60127635D1
Authority
DE
Germany
Prior art keywords
writing
reading
memory
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60127635T
Other languages
English (en)
Other versions
DE60127635T2 (de
Inventor
Takashi Nishihara
Rie Kojima
Noboru Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE60127635D1 publication Critical patent/DE60127635D1/de
Publication of DE60127635T2 publication Critical patent/DE60127635T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Optical Record Carriers And Manufacture Thereof (AREA)
DE60127635T 2000-10-27 2001-10-23 Speicher, Verfahren und Anordnung zum Schreiben und Lesen Expired - Fee Related DE60127635T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000328555 2000-10-27
JP2000328555 2000-10-27

Publications (2)

Publication Number Publication Date
DE60127635D1 true DE60127635D1 (de) 2007-05-16
DE60127635T2 DE60127635T2 (de) 2007-12-27

Family

ID=18805390

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60127635T Expired - Fee Related DE60127635T2 (de) 2000-10-27 2001-10-23 Speicher, Verfahren und Anordnung zum Schreiben und Lesen

Country Status (5)

Country Link
US (1) US6809401B2 (de)
EP (1) EP1202285B1 (de)
CN (1) CN1203550C (de)
DE (1) DE60127635T2 (de)
HK (1) HK1045022A1 (de)

Families Citing this family (44)

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US6507061B1 (en) * 2001-08-31 2003-01-14 Intel Corporation Multiple layer phase-change memory
CN1311553C (zh) * 2001-12-12 2007-04-18 松下电器产业株式会社 非易失性存储器及其制造方法
US20030128646A1 (en) * 2002-01-09 2003-07-10 Peter Nangle Asymmetrical programming mechanism for non-volatile memory
US7151273B2 (en) 2002-02-20 2006-12-19 Micron Technology, Inc. Silver-selenide/chalcogenide glass stack for resistance variable memory
US6849868B2 (en) * 2002-03-14 2005-02-01 Micron Technology, Inc. Methods and apparatus for resistance variable material cells
JP4190238B2 (ja) * 2002-09-13 2008-12-03 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
ATE387726T1 (de) 2002-12-19 2008-03-15 Nxp Bv Phasenwechsel-material enthaltendes elektrisches bauelement
KR100505709B1 (ko) * 2003-09-08 2005-08-03 삼성전자주식회사 상 변화 메모리 장치의 파이어링 방법 및 효율적인파이어링을 수행할 수 있는 상 변화 메모리 장치
KR100564602B1 (ko) * 2003-12-30 2006-03-29 삼성전자주식회사 상 변화 메모리 어레이의 셋 프로그래밍 방법 및 기입드라이버 회로
US7718987B2 (en) * 2004-02-19 2010-05-18 Agency For Science, Technology And Research Electrically writable and erasable memory medium having a data element with two or more multiple-layer structures made of individual layers
DE102004026109A1 (de) * 2004-05-28 2005-12-22 Infineon Technologies Ag Halbleiterspeicherzelle und Verfahren zu deren Herstellung
CN100386882C (zh) * 2004-12-20 2008-05-07 旺宏电子股份有限公司 非易失性存储器及其操作方法
KR100699837B1 (ko) * 2005-04-04 2007-03-27 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 프로그래밍방법
KR100657956B1 (ko) * 2005-04-06 2006-12-14 삼성전자주식회사 다치 저항체 메모리 소자와 그 제조 및 동작 방법
WO2006123305A1 (en) * 2005-05-19 2006-11-23 Koninklijke Philips Electronics N.V. Method for controlling the 'first-to-melt' region in a pcm cell and devices obtained thereof
US7221579B2 (en) * 2005-06-13 2007-05-22 International Business Machines Corporation Method and structure for high performance phase change memory
TWI310558B (en) * 2006-06-02 2009-06-01 Ind Tech Res Inst Phase change memory cell
US7554832B2 (en) * 2006-07-31 2009-06-30 Sandisk 3D Llc Passive element memory array incorporating reversible polarity word line and bit line decoders
US8279704B2 (en) * 2006-07-31 2012-10-02 Sandisk 3D Llc Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
JP5539610B2 (ja) 2007-03-02 2014-07-02 ピーエスフォー ルクスコ エスエイアールエル 相変化メモリのプログラム方法と読み出し方法
US20090039331A1 (en) * 2007-08-07 2009-02-12 International Business Machines Corporation Phase change material structures
JP4595125B2 (ja) 2007-08-31 2010-12-08 独立行政法人産業技術総合研究所 固体メモリ
JP4621897B2 (ja) 2007-08-31 2011-01-26 独立行政法人産業技術総合研究所 固体メモリ
JP5172269B2 (ja) * 2007-10-17 2013-03-27 株式会社東芝 不揮発性半導体記憶装置
JP5063337B2 (ja) * 2007-12-27 2012-10-31 株式会社日立製作所 半導体装置
US8134857B2 (en) * 2008-06-27 2012-03-13 Macronix International Co., Ltd. Methods for high speed reading operation of phase change memory and device employing same
JP5466838B2 (ja) * 2008-07-09 2014-04-09 ピーエスフォー ルクスコ エスエイアールエル 相変化固体メモリの記録材料及び相変化固体メモリ
CN101315811B (zh) * 2008-07-22 2011-06-01 中国科学院上海微系统与信息技术研究所 动态相变存储器
JP4635236B2 (ja) * 2008-10-30 2011-02-23 独立行政法人産業技術総合研究所 固体メモリの製造方法
JP2010171196A (ja) * 2009-01-22 2010-08-05 Elpida Memory Inc 固体メモリ及び半導体装置
JP4599598B2 (ja) 2009-03-04 2010-12-15 独立行政法人産業技術総合研究所 固体メモリ
US20100283029A1 (en) * 2009-05-11 2010-11-11 Charles Dennison Programmable resistance memory and method of making same
US8809829B2 (en) 2009-06-15 2014-08-19 Macronix International Co., Ltd. Phase change memory having stabilized microstructure and manufacturing method
KR101571148B1 (ko) * 2009-09-02 2015-11-23 삼성전자주식회사 저항 메모리 소자의 저항 측정 방법 및 저항 측정 시스템
US7944740B2 (en) * 2009-09-22 2011-05-17 International Business Machines Corporation Multi-level cell programming of PCM by varying the reset amplitude
US8724369B2 (en) 2010-06-18 2014-05-13 Sandisk 3D Llc Composition of memory cell with resistance-switching layers
US8520425B2 (en) 2010-06-18 2013-08-27 Sandisk 3D Llc Resistive random access memory with low current operation
US8395926B2 (en) 2010-06-18 2013-03-12 Sandisk 3D Llc Memory cell with resistance-switching layers and lateral arrangement
CN103078053A (zh) * 2012-12-21 2013-05-01 北京大学 一种多值阻变存储器及其制备方法
US9672906B2 (en) 2015-06-19 2017-06-06 Macronix International Co., Ltd. Phase change memory with inter-granular switching
US9870818B1 (en) * 2016-10-04 2018-01-16 Qualcomm Incorporated Separate read and write address decoding in a memory system to support simultaneous memory read and write operations
FR3084963B1 (fr) 2018-08-08 2022-12-16 Commissariat Energie Atomique Dispositif memoire
FR3084961B1 (fr) 2018-08-08 2021-12-10 Commissariat Energie Atomique Dispositif memoire
FR3107138B1 (fr) 2020-02-06 2022-02-11 Commissariat Energie Atomique Cellule mémoire à changement de phase

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271591A (en) 1963-09-20 1966-09-06 Energy Conversion Devices Inc Symmetrical current controlling device
JPS60164937A (ja) 1984-02-08 1985-08-28 Hitachi Ltd 情報記録媒体
JPH03275382A (ja) 1990-03-27 1991-12-06 Fuji Photo Film Co Ltd 光記録媒体及び記録再生方法
US5296716A (en) 1991-01-18 1994-03-22 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5536947A (en) 1991-01-18 1996-07-16 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom
EP0957477A3 (de) * 1998-05-15 2003-11-05 Matsushita Electric Industrial Co., Ltd. Optisches Aufzeichnungsmedium, Verfahren und Vorrichtung zur Informationsaufzeichnung und -wiedergabe dafür
TWI233098B (en) 2000-08-31 2005-05-21 Matsushita Electric Ind Co Ltd Data recoding medium, the manufacturing method thereof, and the record reproducing method thereof

Also Published As

Publication number Publication date
CN1351379A (zh) 2002-05-29
HK1045022A1 (en) 2002-11-08
EP1202285A3 (de) 2004-01-02
US6809401B2 (en) 2004-10-26
DE60127635T2 (de) 2007-12-27
EP1202285A2 (de) 2002-05-02
EP1202285B1 (de) 2007-04-04
CN1203550C (zh) 2005-05-25
US20020131309A1 (en) 2002-09-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8339 Ceased/non-payment of the annual fee