JP4635236B2 - 固体メモリの製造方法 - Google Patents
固体メモリの製造方法 Download PDFInfo
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- JP4635236B2 JP4635236B2 JP2008280134A JP2008280134A JP4635236B2 JP 4635236 B2 JP4635236 B2 JP 4635236B2 JP 2008280134 A JP2008280134 A JP 2008280134A JP 2008280134 A JP2008280134 A JP 2008280134A JP 4635236 B2 JP4635236 B2 JP 4635236B2
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- Prior art keywords
- recording layer
- solid
- state memory
- film
- phase
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Manufacturing Optical Record Carriers (AREA)
Description
一般的な自己抵抗加熱型の基本構成により相変化RAMを作製した。
実施例1と同様に一般的な自己抵抗加熱型の基本構成により相変化RAMを作製した。成膜時の基板温度を150℃として、記録膜にはGe2Sb7Te8の単層膜を25nm形成した。セルの大きさは、100nm×100nmであった。
Claims (2)
- 相変態により電気特性が変化する記録層を備える固体メモリの製造方法であり、
固体状態間で相変態を生じる膜を2以上隣接して積層させて超格子構造を構成させることにより、前記記録層を形成する記録層形成工程を含み、
前記記録層形成工程を、記録層を構成する前記各層の結晶化相転移温度の中で最も高い温度以上、且つ当該各層の融点の中で一番低い温度以下の範囲内で行い、
前記記録層は、Ge及びSbを含み、Teを主成分としていることを特徴とする固体メモリの製造方法。 - 前記記録層形成工程では、GeTeからなる膜と、Sb2Te3からなる膜とをそれぞれ隣接して積層させることにより、前記記録層を形成することを特徴とする請求項1に記載の固体メモリの製造方法。
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008280134A JP4635236B2 (ja) | 2008-10-30 | 2008-10-30 | 固体メモリの製造方法 |
| US12/998,482 US8530314B2 (en) | 2008-10-30 | 2009-09-28 | Solid-state memory manufacturing method |
| PCT/JP2009/004938 WO2010050118A1 (ja) | 2008-10-30 | 2009-09-28 | 固体メモリの製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008280134A JP4635236B2 (ja) | 2008-10-30 | 2008-10-30 | 固体メモリの製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2010109177A JP2010109177A (ja) | 2010-05-13 |
| JP4635236B2 true JP4635236B2 (ja) | 2011-02-23 |
Family
ID=42128492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008280134A Expired - Fee Related JP4635236B2 (ja) | 2008-10-30 | 2008-10-30 | 固体メモリの製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US8530314B2 (ja) |
| JP (1) | JP4635236B2 (ja) |
| WO (1) | WO2010050118A1 (ja) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160086402A (ko) | 2013-11-15 | 2016-07-19 | 내셔날 인스티튜트 오브 어드밴스드 인더스트리얼 사이언스 앤드 테크놀로지 | 스핀 전자 메모리, 정보 기록 방법 및 정보 재생 방법 |
| KR20160143787A (ko) | 2014-05-12 | 2016-12-14 | 내셔날 인스티튜트 오브 어드밴스드 인더스트리얼 사이언스 앤드 테크놀로지 | 결정 배향층 적층 구조체, 전자 메모리 및 결정 배향층 적층 구조체의 제조 방법 |
| US10543545B2 (en) | 2015-03-16 | 2020-01-28 | National Institute Of Advanced Industrial Science And Technology | Method of initializing multiferroic element |
| WO2023062918A1 (ja) | 2021-10-15 | 2023-04-20 | 国立研究開発法人産業技術総合研究所 | 結晶化積層構造体の製造方法 |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4599598B2 (ja) * | 2009-03-04 | 2010-12-15 | 独立行政法人産業技術総合研究所 | 固体メモリ |
| US8946666B2 (en) * | 2011-06-23 | 2015-02-03 | Macronix International Co., Ltd. | Ge-Rich GST-212 phase change memory materials |
| JP5705689B2 (ja) * | 2011-09-05 | 2015-04-22 | 株式会社アルバック | 相変化メモリの形成方法、及び相変化メモリの形成装置 |
| US8729519B2 (en) | 2012-10-23 | 2014-05-20 | Micron Technology, Inc. | Memory constructions |
| CN103855301B (zh) * | 2012-12-05 | 2016-09-14 | 中国科学院上海微系统与信息技术研究所 | 多级电阻转换存储单元及存储器 |
| CN108539013B (zh) * | 2015-04-27 | 2021-04-27 | 江苏理工学院 | 一种用于高速低功耗相变存储器的Ge/Sb类超晶格相变薄膜材料 |
| US9672906B2 (en) | 2015-06-19 | 2017-06-06 | Macronix International Co., Ltd. | Phase change memory with inter-granular switching |
| US9917252B2 (en) | 2015-06-19 | 2018-03-13 | Macronix International Co., Ltd. | GaSbGe phase change memory materials |
| US11264568B2 (en) | 2016-07-29 | 2022-03-01 | Micron Technology, Inc. | Textured memory cell structures |
| US10050196B1 (en) | 2017-05-04 | 2018-08-14 | Macronix International Co., Ltd. | Dielectric doped, Sb-rich GST phase change memory |
| US11289540B2 (en) | 2019-10-15 | 2022-03-29 | Macronix International Co., Ltd. | Semiconductor device and memory cell |
| US11362276B2 (en) | 2020-03-27 | 2022-06-14 | Macronix International Co., Ltd. | High thermal stability SiOx doped GeSbTe materials suitable for embedded PCM application |
| CN113611798B (zh) * | 2021-07-02 | 2023-08-29 | 深圳大学 | 多层相变薄膜及其相变存储器单元的制备方法 |
| US12310031B2 (en) | 2022-07-08 | 2025-05-20 | Macronix International Co., Ltd. | Multi-layer ovonic threshold switch (OTS) for switching devices and memory devices using the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH066393B2 (ja) * | 1984-03-07 | 1994-01-26 | 株式会社日立製作所 | 情報の記録・消去方法 |
| US6716514B2 (en) * | 1998-01-26 | 2004-04-06 | The Procter & Gamble Company | Disposable article with enhanced texture |
| JP4025527B2 (ja) | 2000-10-27 | 2007-12-19 | 松下電器産業株式会社 | メモリ、書き込み装置、読み出し装置およびその方法 |
| US6809401B2 (en) * | 2000-10-27 | 2004-10-26 | Matsushita Electric Industrial Co., Ltd. | Memory, writing apparatus, reading apparatus, writing method, and reading method |
| WO2005081256A1 (en) * | 2004-02-19 | 2005-09-01 | Agency For Science, Technology And Research | Electrically writeable and erasable memory medium |
| WO2008001411A1 (en) * | 2006-06-23 | 2008-01-03 | Renesas Technology Corp. | Process for producing semiconductor memory device |
| WO2008068807A1 (ja) * | 2006-11-30 | 2008-06-12 | Renesas Technology Corp. | 半導体装置の製造方法および半導体装置 |
| US8017930B2 (en) * | 2006-12-21 | 2011-09-13 | Qimonda Ag | Pillar phase change memory cell |
-
2008
- 2008-10-30 JP JP2008280134A patent/JP4635236B2/ja not_active Expired - Fee Related
-
2009
- 2009-09-28 US US12/998,482 patent/US8530314B2/en not_active Expired - Fee Related
- 2009-09-28 WO PCT/JP2009/004938 patent/WO2010050118A1/ja not_active Ceased
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160086402A (ko) | 2013-11-15 | 2016-07-19 | 내셔날 인스티튜트 오브 어드밴스드 인더스트리얼 사이언스 앤드 테크놀로지 | 스핀 전자 메모리, 정보 기록 방법 및 정보 재생 방법 |
| US9984745B2 (en) | 2013-11-15 | 2018-05-29 | National Institute Of Advanced Industrial Science And Technology | Spin electronic memory, information recording method and information reproducing method |
| KR20160143787A (ko) | 2014-05-12 | 2016-12-14 | 내셔날 인스티튜트 오브 어드밴스드 인더스트리얼 사이언스 앤드 테크놀로지 | 결정 배향층 적층 구조체, 전자 메모리 및 결정 배향층 적층 구조체의 제조 방법 |
| US10090460B2 (en) | 2014-05-12 | 2018-10-02 | National Institute Of Advanced Industrial Science & Technology | Crystal orientation layer laminated structure, electronic memory and method for manufacturing crystal orientation layer laminated structure |
| US10543545B2 (en) | 2015-03-16 | 2020-01-28 | National Institute Of Advanced Industrial Science And Technology | Method of initializing multiferroic element |
| WO2023062918A1 (ja) | 2021-10-15 | 2023-04-20 | 国立研究開発法人産業技術総合研究所 | 結晶化積層構造体の製造方法 |
| KR20240049309A (ko) | 2021-10-15 | 2024-04-16 | 가부시키가이샤 알박 | 결정화 적층 구조체의 제조 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20110207284A1 (en) | 2011-08-25 |
| US8530314B2 (en) | 2013-09-10 |
| WO2010050118A1 (ja) | 2010-05-06 |
| JP2010109177A (ja) | 2010-05-13 |
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