DE60316197D1 - Verfahren und System zum Teilen eines Speichermoduls - Google Patents
Verfahren und System zum Teilen eines SpeichermodulsInfo
- Publication number
- DE60316197D1 DE60316197D1 DE60316197T DE60316197T DE60316197D1 DE 60316197 D1 DE60316197 D1 DE 60316197D1 DE 60316197 T DE60316197 T DE 60316197T DE 60316197 T DE60316197 T DE 60316197T DE 60316197 D1 DE60316197 D1 DE 60316197D1
- Authority
- DE
- Germany
- Prior art keywords
- sharing
- memory module
- module
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US133941 | 1987-12-17 | ||
US10/117,668 US20030088744A1 (en) | 2001-11-06 | 2002-04-04 | Architecture with shared memory |
US117668 | 2002-04-04 | ||
US10/133,941 US7346746B2 (en) | 2002-04-26 | 2002-04-26 | High performance architecture with shared memory |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60316197D1 true DE60316197D1 (de) | 2007-10-18 |
DE60316197T2 DE60316197T2 (de) | 2008-04-10 |
Family
ID=28793881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60316197T Expired - Fee Related DE60316197T2 (de) | 2002-04-04 | 2003-04-04 | Verfahren und System zum Teilen eines Speichermoduls |
Country Status (6)
Country | Link |
---|---|
US (1) | US20060059319A1 (de) |
EP (2) | EP1490764A2 (de) |
KR (1) | KR100701800B1 (de) |
CN (1) | CN1328660C (de) |
DE (1) | DE60316197T2 (de) |
WO (1) | WO2003085524A2 (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7174437B2 (en) * | 2003-10-16 | 2007-02-06 | Silicon Graphics, Inc. | Memory access management in a shared memory multi-processor system |
US7631132B1 (en) * | 2004-12-27 | 2009-12-08 | Unisys Corporation | Method and apparatus for prioritized transaction queuing |
KR100688537B1 (ko) * | 2005-03-16 | 2007-03-02 | 삼성전자주식회사 | 다수개의 프로세서들에 억세스 가능한 메모리 장치를 갖는시스템 |
KR100728650B1 (ko) * | 2005-07-26 | 2007-06-14 | 엠텍비젼 주식회사 | 복수 경로를 통한 다중 분할된 메모리 공유 방법 및 장치 |
KR100658588B1 (ko) * | 2005-11-16 | 2006-12-15 | 엠텍비젼 주식회사 | 메모리 공유 시스템 및 그 방법 |
KR100658591B1 (ko) * | 2005-11-23 | 2006-12-15 | 엠텍비젼 주식회사 | 공유 메모리를 이용한 디스플레이 제어 방법 및 장치 |
WO2007072324A2 (en) * | 2005-12-20 | 2007-06-28 | Nxp B.V. | Multi-processor circuit with shared memory banks |
KR100740635B1 (ko) * | 2005-12-26 | 2007-07-18 | 엠텍비젼 주식회사 | 휴대형 단말기 및 휴대형 단말기에서의 공유 메모리 제어방법 |
KR100700040B1 (ko) * | 2006-03-08 | 2007-03-26 | 엠텍비젼 주식회사 | 공유 메모리를 구비한 장치 및 공유 메모리 억세스 상태정보 제공 방법 |
KR100748191B1 (ko) | 2006-04-06 | 2007-08-09 | 엠텍비젼 주식회사 | 공유 메모리를 구비한 장치 및 공유 메모리 억세스 상태정보 제공 방법 |
KR100843580B1 (ko) * | 2006-05-24 | 2008-07-04 | 엠텍비젼 주식회사 | 접근 권한 레지스터 로직을 갖는 다중 포트 메모리 장치 및그 제어 방법 |
KR100834373B1 (ko) * | 2006-06-05 | 2008-06-02 | 엠텍비젼 주식회사 | 다중 포트 메모리 장치 및 그 접근 권한의 제어 방법 |
KR100855701B1 (ko) * | 2007-01-26 | 2008-09-04 | 엠텍비젼 주식회사 | 복수의 프로세서 코어가 통합된 칩 및 데이터 처리 방법 |
KR101091844B1 (ko) * | 2007-05-17 | 2011-12-12 | 삼성전자주식회사 | 고속으로 배드 블록을 검색하는 플래시 메모리 시스템 및그것의 배드 블록 관리 방법 |
US8239566B2 (en) * | 2008-02-28 | 2012-08-07 | Silicon Graphics International, Corp. | Non-saturating fairness protocol and method for NACKing systems |
CN101706788B (zh) | 2009-11-25 | 2012-11-14 | 惠州Tcl移动通信有限公司 | 一种嵌入式文件系统的跨区访问方法 |
CN101867833A (zh) * | 2010-06-12 | 2010-10-20 | 北京东方艾迪普科技发展有限公司 | 一种视频图像格式转换方法和装置 |
CN103201725B (zh) * | 2010-11-25 | 2015-12-09 | 国际商业机器公司 | 用于在多个处理器之间共享的存储器的存储器访问设备 |
KR20150139718A (ko) | 2014-06-03 | 2015-12-14 | 에스케이하이닉스 주식회사 | 불휘발성 메모리를 제어하는 컨트롤러 및 그것을 포함하는 반도체 장치 |
CN104794065B (zh) * | 2015-05-04 | 2018-01-09 | 常州工学院 | 一种多分组定长数据循环存取方法 |
KR101772921B1 (ko) | 2016-11-25 | 2017-08-30 | 전남대학교 산학협력단 | 메모리 경합 인지를 통한 그래픽 처리 장치의 전력관리 기법 및 그 기법을 수행하는 전력관리 유닛, 그래픽 처리 장치 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3931613A (en) * | 1974-09-25 | 1976-01-06 | Data General Corporation | Data processing system |
US4918587A (en) * | 1987-12-11 | 1990-04-17 | Ncr Corporation | Prefetch circuit for a computer memory subject to consecutive addressing |
US5617575A (en) * | 1991-03-19 | 1997-04-01 | Hitachi, Ltd. | Interprocessor priority control system for multivector processor |
US5412788A (en) * | 1992-04-16 | 1995-05-02 | Digital Equipment Corporation | Memory bank management and arbitration in multiprocessor computer system |
US5809533A (en) * | 1993-02-18 | 1998-09-15 | Unisys Corporation | Dual bus system with multiple processors having data coherency maintenance |
US20030088744A1 (en) * | 2001-11-06 | 2003-05-08 | Infineon Technologies Aktiengesellschaft | Architecture with shared memory |
-
2003
- 2003-04-04 WO PCT/EP2003/003547 patent/WO2003085524A2/en not_active Application Discontinuation
- 2003-04-04 US US10/507,408 patent/US20060059319A1/en not_active Abandoned
- 2003-04-04 CN CNB038067447A patent/CN1328660C/zh not_active Expired - Fee Related
- 2003-04-04 DE DE60316197T patent/DE60316197T2/de not_active Expired - Fee Related
- 2003-04-04 EP EP03745789A patent/EP1490764A2/de not_active Withdrawn
- 2003-04-04 EP EP05025037A patent/EP1628216B1/de not_active Expired - Lifetime
- 2003-04-04 KR KR1020047014737A patent/KR100701800B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
WO2003085524A3 (en) | 2004-08-19 |
KR20040093167A (ko) | 2004-11-04 |
CN1668999A (zh) | 2005-09-14 |
KR100701800B1 (ko) | 2007-04-02 |
EP1490764A2 (de) | 2004-12-29 |
DE60316197T2 (de) | 2008-04-10 |
WO2003085524A2 (en) | 2003-10-16 |
EP1628216B1 (de) | 2007-09-05 |
US20060059319A1 (en) | 2006-03-16 |
EP1628216A3 (de) | 2006-06-21 |
CN1328660C (zh) | 2007-07-25 |
EP1628216A2 (de) | 2006-02-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |