DE602004025941D1 - Einrichtung und verfahren zum speichern von fehleradressen eines halbleiterspeichers - Google Patents

Einrichtung und verfahren zum speichern von fehleradressen eines halbleiterspeichers

Info

Publication number
DE602004025941D1
DE602004025941D1 DE602004025941T DE602004025941T DE602004025941D1 DE 602004025941 D1 DE602004025941 D1 DE 602004025941D1 DE 602004025941 T DE602004025941 T DE 602004025941T DE 602004025941 T DE602004025941 T DE 602004025941T DE 602004025941 D1 DE602004025941 D1 DE 602004025941D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
storing fault
fault addresses
addresses
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004025941T
Other languages
English (en)
Inventor
Gerd Frankowsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE602004025941D1 publication Critical patent/DE602004025941D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory
DE602004025941T 2003-07-21 2004-07-13 Einrichtung und verfahren zum speichern von fehleradressen eines halbleiterspeichers Active DE602004025941D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/624,031 US6937531B2 (en) 2003-07-21 2003-07-21 Memory device and method of storing fail addresses of a memory cell
PCT/EP2004/007740 WO2005015568A1 (en) 2003-07-21 2004-07-13 Memory device and method of storing fail addresses of a memory cell

Publications (1)

Publication Number Publication Date
DE602004025941D1 true DE602004025941D1 (de) 2010-04-22

Family

ID=34079915

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004025941T Active DE602004025941D1 (de) 2003-07-21 2004-07-13 Einrichtung und verfahren zum speichern von fehleradressen eines halbleiterspeichers

Country Status (6)

Country Link
US (1) US6937531B2 (de)
EP (1) EP1647031B1 (de)
KR (1) KR100760052B1 (de)
CN (1) CN1826661A (de)
DE (1) DE602004025941D1 (de)
WO (1) WO2005015568A1 (de)

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KR100555532B1 (ko) * 2003-11-27 2006-03-03 삼성전자주식회사 메모리 테스트 회로 및 테스트 시스템
JP2006179101A (ja) * 2004-12-22 2006-07-06 Fujitsu Ltd 半導体記憶装置
US7518918B2 (en) * 2006-01-31 2009-04-14 International Business Machines Corporation Method and apparatus for repairing embedded memory in an integrated circuit
US20080165599A1 (en) * 2006-01-31 2008-07-10 Gorman Kevin W Design structure used for repairing embedded memory in an integrated circuit
US20090150721A1 (en) * 2007-12-10 2009-06-11 International Business Machines Corporation Utilizing A Potentially Unreliable Memory Module For Memory Mirroring In A Computing System
US8132131B2 (en) * 2007-12-18 2012-03-06 International Business Machines Corporation Design structure including failing address register and compare logic for multi-pass repair of memory arrays
US20090154270A1 (en) * 2007-12-18 2009-06-18 Barth Jr John E Failing address register and compare logic for multi-pass repair of memory arrays
EP2529374A4 (de) * 2010-01-28 2014-04-02 Hewlett Packard Development Co Speicherzugangsverfahren und -vorrichtung
US8739010B2 (en) 2010-11-19 2014-05-27 Altera Corporation Memory array with redundant bits and memory element voting circuits
US9087613B2 (en) 2012-02-29 2015-07-21 Samsung Electronics Co., Ltd. Device and method for repairing memory cell and memory system including the device
US9171605B1 (en) 2012-12-21 2015-10-27 Samsung Electronics Co., Ltd. Concentrated address detecting method of semiconductor device and concentrated address detecting circuit using the same
CN103268237A (zh) * 2013-05-10 2013-08-28 东信和平科技股份有限公司 一种掩膜智能卡的补丁功能扩展方法及装置
WO2016175852A1 (en) * 2015-04-30 2016-11-03 Hewlett Packard Enterprise Development Lp Memory module error tracking
KR102451163B1 (ko) * 2018-02-01 2022-10-06 삼성전자주식회사 반도체 메모리 장치 및 그것의 리페어 방법
DE102020134945A1 (de) 2020-02-27 2021-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Dynamische fehlerüberwachung und -reparatur
US11380415B2 (en) 2020-02-27 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Dynamic error monitor and repair
CN112906332B (zh) * 2021-03-25 2022-08-23 山东高云半导体科技有限公司 Fpga设计的综合实现方法和装置
US11513880B1 (en) * 2021-08-26 2022-11-29 Powerchip Semiconductor Manufacturing Corporation Failure bit count circuit for memory and method thereof
US11984183B2 (en) * 2022-02-01 2024-05-14 Dell Products L.P. Systems and methods for fault-resilient system management random access memory

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414665A (en) * 1979-11-21 1983-11-08 Nippon Telegraph & Telephone Public Corp. Semiconductor memory device test apparatus
GR77678B (de) 1981-09-21 1984-09-25 Hougen Everett D
US4557641A (en) 1983-09-12 1985-12-10 Hougen Everett D Annular cutter
JPS61163110U (de) 1985-03-30 1986-10-09
JPH10289597A (ja) * 1997-04-14 1998-10-27 Advantest Corp メモリ試験装置
JPH11238395A (ja) * 1998-02-20 1999-08-31 Advantest Corp メモリ試験装置
US6072737A (en) * 1998-08-06 2000-06-06 Micron Technology, Inc. Method and apparatus for testing embedded DRAM
TW446955B (en) 1998-10-30 2001-07-21 Siemens Ag The read/write memory with self-testing device and its associated test method
JP4601119B2 (ja) * 2000-05-02 2010-12-22 株式会社アドバンテスト メモリ試験方法・メモリ試験装置
JP3888631B2 (ja) * 2000-11-02 2007-03-07 株式会社ルネサステクノロジ 半導体メモリおよび半導体メモリの検査方法並びに製造方法
US7178072B2 (en) * 2001-06-08 2007-02-13 Renesas Technology America, Inc. Methods and apparatus for storing memory test information
US6862703B2 (en) * 2001-08-13 2005-03-01 Credence Systems Corporation Apparatus for testing memories with redundant storage elements
EP1447813B9 (de) * 2003-02-12 2008-10-22 Infineon Technologies AG Verfahren und MBISR (Memory Built-In Self Repair) zum Reparieren eines Speichers

Also Published As

Publication number Publication date
KR20060040693A (ko) 2006-05-10
CN1826661A (zh) 2006-08-30
WO2005015568A1 (en) 2005-02-17
US6937531B2 (en) 2005-08-30
EP1647031A1 (de) 2006-04-19
US20050018497A1 (en) 2005-01-27
KR100760052B1 (ko) 2007-09-18
EP1647031B1 (de) 2010-03-10

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