DE602005009464D1 - Verfahren und Vorrichtung zum Programmieren eines nichtflüchtigen Speichers - Google Patents

Verfahren und Vorrichtung zum Programmieren eines nichtflüchtigen Speichers

Info

Publication number
DE602005009464D1
DE602005009464D1 DE602005009464T DE602005009464T DE602005009464D1 DE 602005009464 D1 DE602005009464 D1 DE 602005009464D1 DE 602005009464 T DE602005009464 T DE 602005009464T DE 602005009464 T DE602005009464 T DE 602005009464T DE 602005009464 D1 DE602005009464 D1 DE 602005009464D1
Authority
DE
Germany
Prior art keywords
programming
volatile memory
volatile
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005009464T
Other languages
English (en)
Inventor
Liao Yi-Ying
Yeh Chih-Chieh
Tsai Wen-Jer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Macronix International Co Ltd
Original Assignee
Macronix International Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix International Co Ltd filed Critical Macronix International Co Ltd
Publication of DE602005009464D1 publication Critical patent/DE602005009464D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
DE602005009464T 2004-11-19 2005-05-25 Verfahren und Vorrichtung zum Programmieren eines nichtflüchtigen Speichers Active DE602005009464D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62973504P 2004-11-19 2004-11-19
US11/064,316 US7133317B2 (en) 2004-11-19 2005-02-23 Method and apparatus for programming nonvolatile memory

Publications (1)

Publication Number Publication Date
DE602005009464D1 true DE602005009464D1 (de) 2008-10-16

Family

ID=35985227

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005009464T Active DE602005009464D1 (de) 2004-11-19 2005-05-25 Verfahren und Vorrichtung zum Programmieren eines nichtflüchtigen Speichers

Country Status (4)

Country Link
US (1) US7133317B2 (de)
EP (1) EP1659594B1 (de)
DE (1) DE602005009464D1 (de)
TW (1) TWI263223B (de)

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US8482052B2 (en) 2005-01-03 2013-07-09 Macronix International Co., Ltd. Silicon on insulator and thin film transistor bandgap engineered split gate memory
US7473589B2 (en) 2005-12-09 2009-01-06 Macronix International Co., Ltd. Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US8400841B2 (en) * 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7242622B2 (en) * 2005-12-06 2007-07-10 Macronix International Co., Ltd. Methods to resolve hard-to-erase condition in charge trapping non-volatile memory
US7593264B2 (en) * 2006-01-09 2009-09-22 Macronix International Co., Ltd. Method and apparatus for programming nonvolatile memory
US7486560B2 (en) * 2006-06-16 2009-02-03 Macronix International Co., Ltd. Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines
US7505328B1 (en) * 2006-08-14 2009-03-17 Spansion Llc Method and architecture for fast flash memory programming
US7811890B2 (en) 2006-10-11 2010-10-12 Macronix International Co., Ltd. Vertical channel transistor structure and manufacturing method thereof
US8772858B2 (en) 2006-10-11 2014-07-08 Macronix International Co., Ltd. Vertical channel memory and manufacturing method thereof and operating method using the same
US7397705B1 (en) * 2007-02-01 2008-07-08 Macronix International Co., Ltd. Method for programming multi-level cell memory array
US7916551B2 (en) * 2007-11-06 2011-03-29 Macronix International Co., Ltd. Method of programming cell in memory and memory apparatus utilizing the method
KR20090049834A (ko) * 2007-11-14 2009-05-19 삼성전자주식회사 반도체 소자, 그 제조방법 및 동작 방법
US7746705B2 (en) * 2007-12-10 2010-06-29 Spansion Llc Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory
US9240405B2 (en) 2011-04-19 2016-01-19 Macronix International Co., Ltd. Memory with off-chip controller

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Also Published As

Publication number Publication date
TWI263223B (en) 2006-10-01
TW200617967A (en) 2006-06-01
US20060109717A1 (en) 2006-05-25
EP1659594B1 (de) 2008-09-03
US7133317B2 (en) 2006-11-07
EP1659594A1 (de) 2006-05-24

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