DE60015006D1 - Verbindungsschema für Halbleiter-Speicherbauteil - Google Patents

Verbindungsschema für Halbleiter-Speicherbauteil

Info

Publication number
DE60015006D1
DE60015006D1 DE60015006T DE60015006T DE60015006D1 DE 60015006 D1 DE60015006 D1 DE 60015006D1 DE 60015006 T DE60015006 T DE 60015006T DE 60015006 T DE60015006 T DE 60015006T DE 60015006 D1 DE60015006 D1 DE 60015006D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
connection scheme
scheme
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60015006T
Other languages
English (en)
Other versions
DE60015006T2 (de
Inventor
Tsuyoshi Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60015006D1 publication Critical patent/DE60015006D1/de
Publication of DE60015006T2 publication Critical patent/DE60015006T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
DE60015006T 1999-04-19 2000-02-01 Verbindungsschema für Halbleiter-Speicherbauteil Expired - Lifetime DE60015006T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11087999 1999-04-19
JP11087999A JP3913927B2 (ja) 1999-04-19 1999-04-19 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE60015006D1 true DE60015006D1 (de) 2004-11-25
DE60015006T2 DE60015006T2 (de) 2005-06-16

Family

ID=14547021

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60015006T Expired - Lifetime DE60015006T2 (de) 1999-04-19 2000-02-01 Verbindungsschema für Halbleiter-Speicherbauteil

Country Status (6)

Country Link
US (1) US6522004B1 (de)
EP (1) EP1047134B1 (de)
JP (1) JP3913927B2 (de)
KR (1) KR100545494B1 (de)
DE (1) DE60015006T2 (de)
TW (1) TW457646B (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11854973B2 (en) 2021-05-07 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with reduced resistance and method for manufacturing the same

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3652612B2 (ja) 2001-02-20 2005-05-25 松下電器産業株式会社 半導体記憶装置
DE10126566C1 (de) * 2001-05-31 2002-12-05 Infineon Technologies Ag Integrierte Schaltung
JPWO2003044862A1 (ja) * 2001-11-19 2005-03-24 松下電器産業株式会社 半導体装置
JP4868710B2 (ja) * 2004-03-24 2012-02-01 富士通セミコンダクター株式会社 横型ｍｏｓトランジスタ
JP2009283825A (ja) * 2008-05-26 2009-12-03 Toshiba Corp 半導体装置
JP2012019077A (ja) * 2010-07-08 2012-01-26 Toshiba Corp 半導体記憶装置
US8513728B2 (en) * 2011-11-17 2013-08-20 Silicon Storage Technology, Inc. Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates
JP2021141185A (ja) * 2020-03-05 2021-09-16 キオクシア株式会社 半導体記憶装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69129445T2 (de) * 1990-07-23 1998-11-26 Seiko Epson Corp., Tokio/Tokyo Integrierte halbleiterschaltungsanordnung
JP3068378B2 (ja) 1993-08-03 2000-07-24 日本電気アイシーマイコンシステム株式会社 半導体記憶装置
JP3368002B2 (ja) 1993-08-31 2003-01-20 三菱電機株式会社 半導体記憶装置
JP2876963B2 (ja) * 1993-12-15 1999-03-31 日本電気株式会社 半導体装置
JP2785768B2 (ja) 1995-09-14 1998-08-13 日本電気株式会社 半導体装置の製造方法
US5880492A (en) * 1995-10-16 1999-03-09 Xilinx, Inc. Dedicated local line interconnect layout
TW317629B (de) * 1995-11-01 1997-10-11 Samsung Electronics Co Ltd
TW353181B (en) 1996-06-28 1999-02-21 Texas Instruments Inc Circuit with matched delay word line strap
EP0912996B1 (de) 1996-07-18 2002-01-02 Advanced Micro Devices, Inc. Verwendung einer ätzstopschicht in einer integrierten schaltung für die herstellung von versetzt angeordneten leiterbahnen
KR100568075B1 (ko) * 1996-11-26 2006-10-24 가부시끼가이샤 히다치 세이사꾸쇼 반도체집적회로장치

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11854973B2 (en) 2021-05-07 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with reduced resistance and method for manufacturing the same

Also Published As

Publication number Publication date
TW457646B (en) 2001-10-01
KR100545494B1 (ko) 2006-01-25
EP1047134A3 (de) 2002-08-21
KR20000071324A (ko) 2000-11-25
DE60015006T2 (de) 2005-06-16
US6522004B1 (en) 2003-02-18
EP1047134B1 (de) 2004-10-20
JP2000307075A (ja) 2000-11-02
JP3913927B2 (ja) 2007-05-09
EP1047134A2 (de) 2000-10-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE