DE567341T1 - Leistungsanordnung mit isoliertem Gate-Kontakt-Gebiet. - Google Patents

Leistungsanordnung mit isoliertem Gate-Kontakt-Gebiet.

Info

Publication number
DE567341T1
DE567341T1 DE0567341T DE93303169T DE567341T1 DE 567341 T1 DE567341 T1 DE 567341T1 DE 0567341 T DE0567341 T DE 0567341T DE 93303169 T DE93303169 T DE 93303169T DE 567341 T1 DE567341 T1 DE 567341T1
Authority
DE
Germany
Prior art keywords
contact area
insulated gate
gate contact
power arrangement
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE0567341T
Other languages
English (en)
Inventor
Hamza Yilmaz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Publication of DE567341T1 publication Critical patent/DE567341T1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE0567341T 1992-04-23 1993-04-22 Leistungsanordnung mit isoliertem Gate-Kontakt-Gebiet. Pending DE567341T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/873,423 US5430314A (en) 1992-04-23 1992-04-23 Power device with buffered gate shield region

Publications (1)

Publication Number Publication Date
DE567341T1 true DE567341T1 (de) 1994-05-26

Family

ID=25361607

Family Applications (2)

Application Number Title Priority Date Filing Date
DE0567341T Pending DE567341T1 (de) 1992-04-23 1993-04-22 Leistungsanordnung mit isoliertem Gate-Kontakt-Gebiet.
DE69305909T Expired - Fee Related DE69305909T2 (de) 1992-04-23 1993-04-22 Leistungsanordnung mit isoliertem Gate-Kontakt-Gebiet

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69305909T Expired - Fee Related DE69305909T2 (de) 1992-04-23 1993-04-22 Leistungsanordnung mit isoliertem Gate-Kontakt-Gebiet

Country Status (4)

Country Link
US (2) US5430314A (de)
EP (1) EP0567341B1 (de)
JP (1) JP3346825B2 (de)
DE (2) DE567341T1 (de)

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US5686750A (en) * 1991-09-27 1997-11-11 Koshiba & Partners Power semiconductor device having improved reverse recovery voltage
EP0689239B1 (de) * 1994-06-23 2007-03-07 STMicroelectronics S.r.l. Verfahren zur Herstellung von Leistungsbauteilen in MOS-Technologie
US5798538A (en) * 1995-11-17 1998-08-25 International Rectifier Corporation IGBT with integrated control
US5877529A (en) * 1996-04-26 1999-03-02 Megamos Corporation Mosfet termination design and core cell configuration to increase breakdown voltage and to improve device ruggedness
US5912490A (en) * 1997-08-04 1999-06-15 Spectrian MOSFET having buried shield plate for reduced gate/drain capacitance
US5918137A (en) * 1998-04-27 1999-06-29 Spectrian, Inc. MOS transistor with shield coplanar with gate electrode
US6215152B1 (en) * 1998-08-05 2001-04-10 Cree, Inc. MOSFET having self-aligned gate and buried shield and method of making same
US6545316B1 (en) 2000-06-23 2003-04-08 Silicon Wireless Corporation MOSFET devices having linear transfer characteristics when operating in velocity saturation mode and methods of forming and operating same
US6621121B2 (en) * 1998-10-26 2003-09-16 Silicon Semiconductor Corporation Vertical MOSFETs having trench-based gate electrodes within deeper trench-based source electrodes
AU5154300A (en) * 1999-05-28 2000-12-18 Advanced Power Devices, Inc. Discrete schottky diode device with reduced leakage current
JP4122113B2 (ja) * 1999-06-24 2008-07-23 新電元工業株式会社 高破壊耐量電界効果型トランジスタ
US6784486B2 (en) * 2000-06-23 2004-08-31 Silicon Semiconductor Corporation Vertical power devices having retrograded-doped transition regions therein
US6781194B2 (en) * 2001-04-11 2004-08-24 Silicon Semiconductor Corporation Vertical power devices having retrograded-doped transition regions and insulated trench-based electrodes therein
US20030091556A1 (en) * 2000-12-04 2003-05-15 Ruoslahti Erkki I. Methods of inhibiting tumor growth and angiogenesis with anastellin
WO2002084745A2 (en) * 2001-04-11 2002-10-24 Silicon Wireless Corporation Power semiconductor devices and methods of forming same
KR100363101B1 (ko) * 2001-04-16 2002-12-05 페어차일드코리아반도체 주식회사 고내압 아이솔레이션 영역을 갖는 고전압 반도체 소자
ITMI20042243A1 (it) * 2004-11-19 2005-02-19 St Microelectronics Srl Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione
US7875936B2 (en) * 2004-11-19 2011-01-25 Stmicroelectronics, S.R.L. Power MOS electronic device and corresponding realizing method
US7751215B2 (en) 2005-07-08 2010-07-06 Panasonic Corporation Semiconductor device and electric apparatus having a semiconductor layer divided into a plurality of square subregions
JP4185157B2 (ja) 2005-07-25 2008-11-26 松下電器産業株式会社 半導体素子及び電気機器
EP1909326A4 (de) 2005-07-26 2009-05-06 Panasonic Corp Halbleiterelement und elektrische einrichtung
US8552535B2 (en) * 2008-11-14 2013-10-08 Semiconductor Components Industries, Llc Trench shielding structure for semiconductor device and method
WO2010073759A1 (ja) * 2008-12-25 2010-07-01 三菱電機株式会社 電力用半導体装置
US20130341673A1 (en) * 2012-06-21 2013-12-26 Infineon Technologies Ag Reverse Conducting IGBT
US9362349B2 (en) 2012-06-21 2016-06-07 Infineon Technologies Ag Semiconductor device with charge carrier lifetime reduction means
US9214521B2 (en) 2012-06-21 2015-12-15 Infineon Technologies Ag Reverse conducting IGBT
US9871134B2 (en) * 2015-12-21 2018-01-16 Taiwan Semiconductor Manufacturing Company Ltd. Power MOSFETs and methods for manufacturing the same

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US4532534A (en) * 1982-09-07 1985-07-30 Rca Corporation MOSFET with perimeter channel
US4789882A (en) * 1983-03-21 1988-12-06 International Rectifier Corporation High power MOSFET with direct connection from connection pads to underlying silicon
JPS60249367A (ja) * 1984-05-25 1985-12-10 Hitachi Ltd 絶縁ゲ−ト形トランジスタ
JPS6180860A (ja) * 1984-09-28 1986-04-24 Hitachi Ltd パワ−mosfet
JPS6184865A (ja) * 1984-10-02 1986-04-30 Nec Corp 半導体装置
US4985739A (en) * 1984-10-05 1991-01-15 Analog Devices, Incorporated Low-leakage JFET
US4631564A (en) * 1984-10-23 1986-12-23 Rca Corporation Gate shield structure for power MOS device
JPS61182264A (ja) * 1985-02-08 1986-08-14 Nissan Motor Co Ltd 縦型mosトランジスタ
JPS6373564A (ja) * 1986-09-16 1988-04-04 Toshiba Corp 半導体装置
JPS6384070A (ja) * 1986-09-26 1988-04-14 Mitsubishi Electric Corp 電界効果型半導体装置
EP0293846A1 (de) * 1987-06-05 1988-12-07 Siemens Aktiengesellschaft MIS-Leistunsgstransistor
JP2771172B2 (ja) * 1988-04-01 1998-07-02 日本電気株式会社 縦型電界効果トランジスタ
JP2785271B2 (ja) * 1988-04-28 1998-08-13 富士電機株式会社 半導体装置
JPH0235780A (ja) * 1988-07-26 1990-02-06 Matsushita Electron Corp 縦型mos電界効果トランジスタ
JPH0282534A (ja) * 1988-09-19 1990-03-23 Sanyo Electric Co Ltd 縦型mosfet及びその製造方法
EP0416805B1 (de) * 1989-08-30 1996-11-20 Siliconix, Inc. Transistor mit Spannungsbegrenzungsanordnung
JPH03173180A (ja) * 1989-12-01 1991-07-26 Hitachi Ltd 半導体素子

Also Published As

Publication number Publication date
EP0567341A1 (de) 1993-10-27
EP0567341B1 (de) 1996-11-13
DE69305909D1 (de) 1996-12-19
JPH07115193A (ja) 1995-05-02
US5430314A (en) 1995-07-04
DE69305909T2 (de) 1997-03-13
JP3346825B2 (ja) 2002-11-18
US5445978A (en) 1995-08-29

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