DE4432925C2 - Halbleiterspeichervorrichtung - Google Patents

Halbleiterspeichervorrichtung

Info

Publication number
DE4432925C2
DE4432925C2 DE4432925A DE4432925A DE4432925C2 DE 4432925 C2 DE4432925 C2 DE 4432925C2 DE 4432925 A DE4432925 A DE 4432925A DE 4432925 A DE4432925 A DE 4432925A DE 4432925 C2 DE4432925 C2 DE 4432925C2
Authority
DE
Germany
Prior art keywords
signal
level
address
equalization
response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE4432925A
Other languages
German (de)
English (en)
Other versions
DE4432925A1 (de
Inventor
Kiyohiro Furutani
Tadaaki Yamauchi
Makiko Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE4432925A1 publication Critical patent/DE4432925A1/de
Application granted granted Critical
Publication of DE4432925C2 publication Critical patent/DE4432925C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE4432925A 1993-09-17 1994-09-15 Halbleiterspeichervorrichtung Expired - Fee Related DE4432925C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5231701A JPH0785675A (ja) 1993-09-17 1993-09-17 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE4432925A1 DE4432925A1 (de) 1995-03-23
DE4432925C2 true DE4432925C2 (de) 1999-06-24

Family

ID=16927652

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4432925A Expired - Fee Related DE4432925C2 (de) 1993-09-17 1994-09-15 Halbleiterspeichervorrichtung

Country Status (4)

Country Link
US (2) US5487043A (cg-RX-API-DMAC7.html)
JP (1) JPH0785675A (cg-RX-API-DMAC7.html)
DE (1) DE4432925C2 (cg-RX-API-DMAC7.html)
TW (1) TW257868B (cg-RX-API-DMAC7.html)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525971B2 (en) * 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US5729503A (en) * 1994-12-23 1998-03-17 Micron Technology, Inc. Address transition detection on a synchronous design
US5610864A (en) 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
US5719813A (en) * 1995-06-06 1998-02-17 Micron Technology, Inc. Cell plate referencing for DRAM sensing
US5654933A (en) * 1995-06-30 1997-08-05 Micron Technology, Inc. Equilibrated sam read transfer circuit
JP3225813B2 (ja) * 1995-11-20 2001-11-05 富士通株式会社 半導体記憶装置
KR0166843B1 (ko) * 1995-12-27 1999-02-01 문정환 저소비 전력의 디램 비트라인 선택회로
US7681005B1 (en) 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
JPH09231783A (ja) * 1996-02-26 1997-09-05 Sharp Corp 半導体記憶装置
JP3497650B2 (ja) * 1996-02-27 2004-02-16 株式会社東芝 半導体メモリ装置
JPH09265778A (ja) * 1996-03-29 1997-10-07 Oki Micro Design Miyazaki:Kk シンクロナスｄｒａｍ
KR100218307B1 (ko) * 1996-07-01 1999-09-01 구본준 반도체 메모리소자의 칼럼디코딩회로
US6981126B1 (en) 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
US6401186B1 (en) 1996-07-03 2002-06-04 Micron Technology, Inc. Continuous burst memory which anticipates a next requested start address
DE69627350D1 (de) * 1996-11-27 2003-05-15 St Microelectronics Srl Verfahren und Vorrichtung zur Erzeugung eines Addressenübergangssynchronisationsignals (ATD)
US5970022A (en) * 1997-03-21 1999-10-19 Winbond Electronics Corporation Semiconductor memory device with reduced read disturbance
JP4221764B2 (ja) * 1997-04-25 2009-02-12 沖電気工業株式会社 半導体記憶装置
US5943288A (en) * 1997-10-31 1999-08-24 Integrated Silicon Solution, Inc. Apparatus and method for minimizing address hold time in asynchronous SRAM
US6072738A (en) * 1998-03-09 2000-06-06 Lsi Logic Corporation Cycle time reduction using an early precharge
DE19844479C1 (de) 1998-09-28 2000-04-13 Siemens Ag Integrierter Speicher mit einem differentiellen Leseverstärker
US6301175B1 (en) 2000-07-26 2001-10-09 Micron Technology, Inc. Memory device with single-ended sensing and low voltage pre-charge
US6292417B1 (en) 2000-07-26 2001-09-18 Micron Technology, Inc. Memory device with reduced bit line pre-charge voltage
US6396308B1 (en) * 2001-02-27 2002-05-28 Sun Microsystems, Inc. Sense amplifier with dual linearly weighted inputs and offset voltage correction
US6738301B2 (en) 2002-08-29 2004-05-18 Micron Technology, Inc. Method and system for accelerating coupling of digital signals
KR100535131B1 (ko) * 2003-05-30 2005-12-07 주식회사 하이닉스반도체 페이지 모드에서의 메모리 소자 리드 방법 및 이를 이용한로우 디코더 제어회로
US8107308B2 (en) * 2009-01-13 2012-01-31 Samsung Electronics Co., Ltd. Semiconductor memory device
JP2013239222A (ja) * 2012-05-15 2013-11-28 Ps4 Luxco S A R L 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2892757B2 (ja) * 1990-03-23 1999-05-17 三菱電機株式会社 半導体集積回路装置
JP2748053B2 (ja) * 1991-07-23 1998-05-06 三菱電機株式会社 半導体記憶装置
JP2667946B2 (ja) * 1992-09-21 1997-10-27 三菱電機株式会社 半導体記憶装置
JP3476231B2 (ja) * 1993-01-29 2003-12-10 三菱電機エンジニアリング株式会社 同期型半導体記憶装置および半導体記憶装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, Dezember 1984, S. 1008-1013 *

Also Published As

Publication number Publication date
JPH0785675A (ja) 1995-03-31
US5640363A (en) 1997-06-17
TW257868B (cg-RX-API-DMAC7.html) 1995-09-21
US5487043A (en) 1996-01-23
DE4432925A1 (de) 1995-03-23

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee