DE4112416C2 - - Google Patents

Info

Publication number
DE4112416C2
DE4112416C2 DE4112416A DE4112416A DE4112416C2 DE 4112416 C2 DE4112416 C2 DE 4112416C2 DE 4112416 A DE4112416 A DE 4112416A DE 4112416 A DE4112416 A DE 4112416A DE 4112416 C2 DE4112416 C2 DE 4112416C2
Authority
DE
Germany
Prior art keywords
coating
galvanic
matrix
copper alloy
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE4112416A
Other languages
German (de)
English (en)
Other versions
DE4112416A1 (de
Inventor
Hisatosi Sagamihara Kanagawa Jp Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2287333A external-priority patent/JP2542735B2/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE4112416A1 publication Critical patent/DE4112416A1/de
Application granted granted Critical
Publication of DE4112416C2 publication Critical patent/DE4112416C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H10W70/457—Materials of metallic layers on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S205/00—Electrolysis: processes, compositions used therein, and methods of preparing the compositions
    • Y10S205/92—Electrolytic coating of circuit board or printed circuit, other than selected area coating

Landscapes

  • Electroplating Methods And Accessories (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Solid-Phase Diffusion Into Metallic Material Surfaces (AREA)
  • Lead Frames For Integrated Circuits (AREA)
DE4112416A 1990-04-16 1991-04-16 Leiterrahmenmaterial fuer einen halbleiter und verfahren zur herstellung des leiterrahmenmaterials Granted DE4112416A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9762690 1990-04-16
JP10621590 1990-04-21
JP2287333A JP2542735B2 (ja) 1990-04-16 1990-10-26 半導体リ―ドフレ―ム材料及びその製造方法

Publications (2)

Publication Number Publication Date
DE4112416A1 DE4112416A1 (de) 1991-10-17
DE4112416C2 true DE4112416C2 (https=) 1993-04-29

Family

ID=27308452

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4112416A Granted DE4112416A1 (de) 1990-04-16 1991-04-16 Leiterrahmenmaterial fuer einen halbleiter und verfahren zur herstellung des leiterrahmenmaterials

Country Status (2)

Country Link
US (1) US5167794A (https=)
DE (1) DE4112416A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3444981B2 (ja) * 1994-08-29 2003-09-08 忠弘 大見 リードフレーム及びリードフレーム用素材
US5480519A (en) * 1995-02-06 1996-01-02 Texas Instruments Incorporated Electrochemical etch system and method
US5529682A (en) * 1995-06-26 1996-06-25 Motorola, Inc. Method for making semiconductor devices having electroplated leads
US6087714A (en) * 1998-04-27 2000-07-11 Matsushita Electric Industrial Co., Ltd. Semiconductor devices having tin-based solder film containing no lead and process for producing the devices
US6156680A (en) * 1998-12-23 2000-12-05 Bba Nonwovens Simpsonville, Inc. Reverse osmosis support substrate and method for its manufacture
SG87194A1 (en) * 2000-08-17 2002-03-19 Samsung Techwin Co Ltd Lead frame and method of manufacturing the lead frame
KR100378485B1 (ko) * 2000-08-17 2003-03-29 삼성테크윈 주식회사 리드 프레임과 이의 제조방법
US20080001264A1 (en) * 2006-07-03 2008-01-03 Texas Instruments Incorporated Exposed top side copper leadframe manufacturing
JP5940257B2 (ja) * 2011-08-01 2016-06-29 株式会社三井ハイテック リードフレーム及びリードフレームの製造方法並びにこれを用いた半導体装置
US9607933B2 (en) * 2014-02-07 2017-03-28 Dawning Leading Technology Inc. Lead frame structure for quad flat no-lead package, quad flat no-lead package and method for forming the lead frame structure
US10062639B2 (en) * 2014-12-10 2018-08-28 Stmicroelectronics Sdn Bhd Integrated circuit device with plating on lead interconnection point and method of forming the device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3157539A (en) * 1961-09-28 1964-11-17 Dreher Manfrid Method of producing shaped metallic bodies having a copper alloy base and a noble metal outer coating
US4270986A (en) * 1979-07-12 1981-06-02 Sifco Industries, Inc. Method for soldering aluminum
JPS5757885A (en) * 1980-09-19 1982-04-07 Hitachi Cable Ltd Heat resistant silver coated conductor
JPS5757886A (en) * 1980-09-24 1982-04-07 Hitachi Cable Ltd Heat resistant silver coated conductor
JPS5887229A (ja) * 1981-11-19 1983-05-25 Nippon Gakki Seizo Kk リ−ドフレ−ム用板材の製法
DE3206262C2 (de) * 1982-02-20 1986-02-13 Doduco KG Dr. Eugen Dürrwächter, 7530 Pforzheim Verfahren zur Herstellung von galvanisch selektiv mit Edelmetall beschichteten Bändern als Halbzeug für elektrische Kontakte
JPH0674496B2 (ja) * 1987-07-13 1994-09-21 株式会社神戸製鋼所 リードフレーム材料の製造方法
JPH01257356A (ja) * 1988-04-07 1989-10-13 Kobe Steel Ltd 半導体用リードフレーム

Also Published As

Publication number Publication date
US5167794A (en) 1992-12-01
DE4112416A1 (de) 1991-10-17

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee