DE4013143A1 - Selektives (cvd)-verfahren und geraet dafuer - Google Patents

Selektives (cvd)-verfahren und geraet dafuer

Info

Publication number
DE4013143A1
DE4013143A1 DE4013143A DE4013143A DE4013143A1 DE 4013143 A1 DE4013143 A1 DE 4013143A1 DE 4013143 A DE4013143 A DE 4013143A DE 4013143 A DE4013143 A DE 4013143A DE 4013143 A1 DE4013143 A1 DE 4013143A1
Authority
DE
Germany
Prior art keywords
gas
wafer
layer
reaction chamber
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE4013143A
Other languages
German (de)
English (en)
Other versions
DE4013143C2 (enExample
Inventor
Kunio Saito
Yoshinobu Arita
Takao Amazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE4013143A1 publication Critical patent/DE4013143A1/de
Application granted granted Critical
Publication of DE4013143C2 publication Critical patent/DE4013143C2/de
Granted legal-status Critical Current

Links

Classifications

    • H01L21/205—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
    • C23C16/0236—Pretreatment of the material to be coated by cleaning or etching by etching with a reactive gas
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
DE4013143A 1989-04-21 1990-04-20 Selektives (cvd)-verfahren und geraet dafuer Granted DE4013143A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10007889 1989-04-21
JP20782989 1989-08-14

Publications (2)

Publication Number Publication Date
DE4013143A1 true DE4013143A1 (de) 1990-10-31
DE4013143C2 DE4013143C2 (enExample) 1992-07-09

Family

ID=26441167

Family Applications (1)

Application Number Title Priority Date Filing Date
DE4013143A Granted DE4013143A1 (de) 1989-04-21 1990-04-20 Selektives (cvd)-verfahren und geraet dafuer

Country Status (4)

Country Link
US (1) US5104694A (enExample)
JP (1) JP2939500B2 (enExample)
KR (1) KR940001885B1 (enExample)
DE (1) DE4013143A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2675309A1 (fr) * 1991-03-22 1992-10-16 Siemens Ag Procede pour eliminer localement des couches isolantes transparentes aux ultraviolets, situees sur un substrat semiconducteur.
EP0606751A1 (en) * 1993-01-13 1994-07-20 Applied Materials, Inc. Method for depositing polysilicon films having improved uniformity and apparatus therefor
DE4238080C2 (de) * 1991-11-11 2002-10-31 Mitsubishi Electric Corp Verbindungsstruktur für leitende Schichten einer Halbleitervorrichtung und ein Verfahren zu deren Herstellung
DE4326211B4 (de) * 1992-08-07 2005-02-03 Micron Technology, Inc. Chemisches Bedampfungsverfahren zum Herstellen einer Konformen Schicht aus Titansilicid auf einem Halbleiterwafer

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3469251B2 (ja) * 1990-02-14 2003-11-25 株式会社東芝 半導体装置の製造方法
US5284521A (en) * 1990-09-21 1994-02-08 Anelva Corporation Vacuum film forming apparatus
TW203633B (enExample) * 1991-06-03 1993-04-11 L Air Liquide Sa Pour L Expl Des Proce
JP3109687B2 (ja) * 1992-03-09 2000-11-20 三菱電機株式会社 半導体装置の導電層接続構造の製造方法
US5393565A (en) * 1992-06-08 1995-02-28 Fujitsu Limited Method for deposition of a refractory metal nitride and method for formation of a conductive film containing a refractory metal nitride
US5652180A (en) * 1993-06-28 1997-07-29 Kawasaki Steel Corporation Method of manufacturing semiconductor device with contact structure
DE69421465T2 (de) * 1993-07-30 2000-02-10 Applied Materials, Inc. Verfahren zur Ablagerung von Silzium-Nitrid auf Siliziumoberflächen
JPH07176627A (ja) * 1993-12-17 1995-07-14 Nec Corp 半導体装置の製造方法
JPH08191054A (ja) * 1995-01-10 1996-07-23 Kawasaki Steel Corp 半導体装置及びその製造方法
US6001729A (en) * 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
EP0805697B1 (en) * 1995-02-09 2002-06-26 Puritan-Bennett Corporation Piston based ventilator
KR100224654B1 (ko) * 1995-09-19 1999-10-15 윤종용 반도체장치의 커패시터 형성방법
KR100269311B1 (ko) * 1997-10-10 2000-10-16 윤종용 웨이퍼스트립방법
US5856237A (en) * 1997-10-20 1999-01-05 Industrial Technology Research Institute Insitu formation of TiSi2/TiN bi-layer structures using self-aligned nitridation treatment on underlying CVD-TiSi2 layer
US6068441A (en) * 1997-11-21 2000-05-30 Asm America, Inc. Substrate transfer system for semiconductor processing equipment
US6293749B1 (en) 1997-11-21 2001-09-25 Asm America, Inc. Substrate transfer system for semiconductor processing equipment
US6019839A (en) * 1998-04-17 2000-02-01 Applied Materials, Inc. Method and apparatus for forming an epitaxial titanium silicide film by low pressure chemical vapor deposition
US6429101B1 (en) * 1999-01-29 2002-08-06 International Business Machines Corporation Method of forming thermally stable polycrystal to single crystal electrical contact structure
US6494959B1 (en) 2000-01-28 2002-12-17 Applied Materials, Inc. Process and apparatus for cleaning a silicon surface
KR100517911B1 (ko) * 2000-05-19 2005-10-04 주식회사 하이닉스반도체 하부전극과 스토리지 노드 콘택간의 오정렬 및확산방지막의 산화를 방지할 수 있는 반도체 장치 제조 방법
JP3626115B2 (ja) * 2001-06-14 2005-03-02 沖電気工業株式会社 チタン化合物を含有するｃｖｄチタン膜の形成方法
KR100434698B1 (ko) * 2001-09-05 2004-06-07 주식회사 하이닉스반도체 반도체소자의 선택적 에피성장법
CN100428400C (zh) * 2002-07-24 2008-10-22 应用材料股份有限公司 热隔离加热处理室的设备及方法
KR100725098B1 (ko) * 2005-11-17 2007-06-04 삼성전자주식회사 반도체 제조설비의 유량조절기 오동작 감지장치 및 그 방법
US8362503B2 (en) * 2007-03-09 2013-01-29 Cree, Inc. Thick nitride semiconductor structures with interlayer structures
JP5250470B2 (ja) * 2009-04-22 2013-07-31 株式会社日立ハイテクノロジーズ 試料ホールダ，該試料ホールダの使用法、及び荷電粒子装置
TW201117297A (en) * 2009-07-31 2011-05-16 Ulvac Inc Semiconductor device manufacturing apparatus and semiconductor device manufacturing method
DE102011080202A1 (de) * 2011-08-01 2013-02-07 Gebr. Schmid Gmbh Vorrichtung und Verfahren zur Herstellung von dünnen Schichten
US11942365B2 (en) * 2017-06-02 2024-03-26 Eugenus, Inc. Multi-region diffusion barrier containing titanium, silicon and nitrogen
US10535527B2 (en) * 2017-07-13 2020-01-14 Applied Materials, Inc. Methods for depositing semiconductor films
US20220084842A1 (en) * 2020-09-11 2022-03-17 Applied Materials, Inc. Antifragile systems for semiconductor processing equipment using multiple special sensors and algorithms

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4501769A (en) * 1982-03-30 1985-02-26 Siemens Aktiengesellschaft Method for selective deposition of layer structures consisting of silicides of HMP metals on silicon substrates and products so-formed
GB2148946A (en) * 1983-10-31 1985-06-05 Advanced Semiconductor Mat Metal-silicide deposition using plasma-enhanced chemical vapour deposition
US4668530A (en) * 1985-07-23 1987-05-26 Massachusetts Institute Of Technology Low pressure chemical vapor deposition of refractory metal silicides

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112611A (ja) * 1982-12-17 1984-06-29 Matsushita Electric Ind Co Ltd 気相成長装置
US4629635A (en) * 1984-03-16 1986-12-16 Genus, Inc. Process for depositing a low resistivity tungsten silicon composite film on a substrate
US4647494A (en) * 1985-10-31 1987-03-03 International Business Machines Corporation Silicon/carbon protection of metallic magnetic structures
GB2195663B (en) * 1986-08-15 1990-08-22 Nippon Telegraph & Telephone Chemical vapour deposition method and apparatus therefor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4501769A (en) * 1982-03-30 1985-02-26 Siemens Aktiengesellschaft Method for selective deposition of layer structures consisting of silicides of HMP metals on silicon substrates and products so-formed
GB2148946A (en) * 1983-10-31 1985-06-05 Advanced Semiconductor Mat Metal-silicide deposition using plasma-enhanced chemical vapour deposition
US4668530A (en) * 1985-07-23 1987-05-26 Massachusetts Institute Of Technology Low pressure chemical vapor deposition of refractory metal silicides

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP 63-0 33 569 A.:Pat. Abstr. of Japan C-510, 8.7.1988, Vol. 12, No. 242 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2675309A1 (fr) * 1991-03-22 1992-10-16 Siemens Ag Procede pour eliminer localement des couches isolantes transparentes aux ultraviolets, situees sur un substrat semiconducteur.
DE4238080C2 (de) * 1991-11-11 2002-10-31 Mitsubishi Electric Corp Verbindungsstruktur für leitende Schichten einer Halbleitervorrichtung und ein Verfahren zu deren Herstellung
DE4326211B4 (de) * 1992-08-07 2005-02-03 Micron Technology, Inc. Chemisches Bedampfungsverfahren zum Herstellen einer Konformen Schicht aus Titansilicid auf einem Halbleiterwafer
EP0606751A1 (en) * 1993-01-13 1994-07-20 Applied Materials, Inc. Method for depositing polysilicon films having improved uniformity and apparatus therefor
US5576059A (en) * 1993-01-13 1996-11-19 Applied Materials, Inc. Depositing polysilicon films having improved uniformity and apparatus therefor
US6402850B1 (en) 1993-01-13 2002-06-11 Applied Materials, Inc. Depositing polysilicon films having improved uniformity and apparatus therefor

Also Published As

Publication number Publication date
KR900017107A (ko) 1990-11-15
JP2939500B2 (ja) 1999-08-25
US5104694A (en) 1992-04-14
JPH03224223A (ja) 1991-10-03
DE4013143C2 (enExample) 1992-07-09
KR940001885B1 (ko) 1994-03-10

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee