DE3902701C2 - - Google Patents

Info

Publication number
DE3902701C2
DE3902701C2 DE3902701A DE3902701A DE3902701C2 DE 3902701 C2 DE3902701 C2 DE 3902701C2 DE 3902701 A DE3902701 A DE 3902701A DE 3902701 A DE3902701 A DE 3902701A DE 3902701 C2 DE3902701 C2 DE 3902701C2
Authority
DE
Germany
Prior art keywords
film
trench
sio
cvd
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3902701A
Other languages
German (de)
English (en)
Other versions
DE3902701A1 (de
Inventor
Hiroomi Yokohama Jp Nakajima
Nobuyuki Tokio/Tokyo Jp Itoh
Hiroyuki Ayase Kanagawa Jp Nihira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2029888A external-priority patent/JPH01196134A/ja
Priority claimed from JP63078748A external-priority patent/JP2763105B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3902701A1 publication Critical patent/DE3902701A1/de
Application granted granted Critical
Publication of DE3902701C2 publication Critical patent/DE3902701C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Element Separation (AREA)
DE3902701A 1988-01-30 1989-01-30 Verfahren zur herstellung einer halbleiteranordnung Granted DE3902701A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2029888A JPH01196134A (ja) 1988-01-30 1988-01-30 半導体装置の製造方法
JP63078748A JP2763105B2 (ja) 1988-03-31 1988-03-31 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3902701A1 DE3902701A1 (de) 1989-08-10
DE3902701C2 true DE3902701C2 (enFirst) 1993-07-29

Family

ID=26357214

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3902701A Granted DE3902701A1 (de) 1988-01-30 1989-01-30 Verfahren zur herstellung einer halbleiteranordnung

Country Status (2)

Country Link
US (1) US4931409A (enFirst)
DE (1) DE3902701A1 (enFirst)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5332683A (en) * 1989-06-14 1994-07-26 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device having elements isolated by trench
US5183775A (en) * 1990-01-23 1993-02-02 Applied Materials, Inc. Method for forming capacitor in trench of semiconductor wafer by implantation of trench surfaces with oxygen
KR960006714B1 (ko) * 1990-05-28 1996-05-22 가부시끼가이샤 도시바 반도체 장치의 제조 방법
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5177580A (en) * 1991-01-22 1993-01-05 Santa Barbara Research Center Implant guarded mesa having improved detector uniformity
US5192708A (en) * 1991-04-29 1993-03-09 International Business Machines Corporation Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5217919A (en) * 1992-03-19 1993-06-08 Harris Corporation Method of forming island with polysilicon-filled trench isolation
JP2955459B2 (ja) * 1993-12-20 1999-10-04 株式会社東芝 半導体装置の製造方法
JP3400846B2 (ja) * 1994-01-20 2003-04-28 三菱電機株式会社 トレンチ構造を有する半導体装置およびその製造方法
JP3396553B2 (ja) * 1994-02-04 2003-04-14 三菱電機株式会社 半導体装置の製造方法及び半導体装置
KR100464383B1 (ko) * 1997-05-26 2005-02-28 삼성전자주식회사 트렌치소자분리를이용한반도체장치
US6057209A (en) * 1997-07-10 2000-05-02 Advanced Micro Devices, Inc. Semiconductor device having a nitrogen bearing isolation region
US6355540B2 (en) * 1998-07-27 2002-03-12 Acer Semicondutor Manufacturing Inc. Stress-free shallow trench isolation
US6144086A (en) * 1999-04-30 2000-11-07 International Business Machines Corporation Structure for improved latch-up using dual depth STI with impurity implant
JP3917327B2 (ja) * 1999-06-01 2007-05-23 株式会社ルネサステクノロジ 半導体装置の製造方法及び装置
US20030235957A1 (en) * 2002-06-25 2003-12-25 Samir Chaudhry Method and structure for graded gate oxides on vertical and non-planar surfaces
KR100327348B1 (en) * 2000-07-26 2002-03-06 Samsung Electronics Co Ltd Semiconductor capable of decreasing junction leakage current and narrow width effect and fabricating method thereof
US6660642B2 (en) 2001-07-25 2003-12-09 Chartered Semiconductor Manufacturing Ltd. Toxic residual gas removal by non-reactive ion sputtering
KR100540371B1 (ko) * 2004-03-02 2006-01-11 이태복 고 내압용 반도체 소자 및 그 제조방법
US7129149B1 (en) 2004-06-07 2006-10-31 Integrated Device Technology, Inc. Method for forming shallow trench isolation structure with anti-reflective liner
US7176104B1 (en) 2004-06-08 2007-02-13 Integrated Device Technology, Inc. Method for forming shallow trench isolation structure with deep oxide region
US7547945B2 (en) * 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7384849B2 (en) * 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7859026B2 (en) * 2006-03-16 2010-12-28 Spansion Llc Vertical semiconductor device
US7982284B2 (en) * 2006-06-28 2011-07-19 Infineon Technologies Ag Semiconductor component including an isolation structure and a contact to the substrate
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) * 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) * 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
JP2009238980A (ja) * 2008-03-27 2009-10-15 Hitachi Ltd 半導体装置及びその製造方法
US10522549B2 (en) * 2018-02-17 2019-12-31 Varian Semiconductor Equipment Associates, Inc. Uniform gate dielectric for DRAM device

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5388584A (en) * 1977-01-17 1978-08-04 Hitachi Ltd Production of sio2 layer for interelement isolation
DE3265339D1 (en) * 1981-03-20 1985-09-19 Toshiba Kk Method for manufacturing semiconductor device
JPS6059302B2 (ja) * 1981-05-26 1985-12-24 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション 多量の酸素を用いた反応性イオン食刻法
US4493740A (en) * 1981-06-01 1985-01-15 Matsushita Electric Industrial Company, Limited Method for formation of isolation oxide regions in semiconductor substrates
US4519128A (en) * 1983-10-05 1985-05-28 International Business Machines Corporation Method of making a trench isolated device
JPH073858B2 (ja) * 1984-04-11 1995-01-18 株式会社日立製作所 半導体装置の製造方法
US4534824A (en) * 1984-04-16 1985-08-13 Advanced Micro Devices, Inc. Process for forming isolation slots having immunity to surface inversion
US4703554A (en) * 1985-04-04 1987-11-03 Texas Instruments Incorporated Technique for fabricating a sidewall base contact with extrinsic base-on-insulator
US4660278A (en) * 1985-06-26 1987-04-28 Texas Instruments Incorporated Process of making IC isolation structure
JPH0637326B2 (ja) * 1985-07-05 1994-05-18 株式会社ニッカト− 熱交換器の伝熱用部材
EP0231740A3 (en) * 1986-01-30 1989-07-12 Texas Instruments Incorporated A polysilicon self-aligned bipolar device and process of manufacturing same
JPS62298110A (ja) * 1986-06-18 1987-12-25 Matsushita Electric Ind Co Ltd 半導体集積回路の製造方法
US4766090A (en) * 1986-04-21 1988-08-23 American Telephone And Telegraph Company, At&T Bell Laboratories Methods for fabricating latchup-preventing CMOS device
US4693781A (en) * 1986-06-26 1987-09-15 Motorola, Inc. Trench formation process
JPH07120754B2 (ja) * 1986-10-15 1995-12-20 三菱電機株式会社 半導体装置の製造方法
JPS63114158A (ja) * 1986-10-30 1988-05-19 Sony Corp 半導体装置の製造方法
JPS63287024A (ja) * 1987-05-19 1988-11-24 Seiko Epson Corp 半導体装置の製造方法
JPS63314844A (ja) * 1987-06-18 1988-12-22 Toshiba Corp 半導体装置の製造方法
GB2207281B (en) * 1987-07-24 1992-02-05 Plessey Co Plc A method of providing refilled trenches

Also Published As

Publication number Publication date
US4931409A (en) 1990-06-05
DE3902701A1 (de) 1989-08-10

Similar Documents

Publication Publication Date Title
DE3902701C2 (enFirst)
DE69320520T2 (de) Verfahren zur Herstellung eines Heteroübergangsbipolartransistors
EP0000897B1 (de) Verfahren zum Herstellen von lateral isolierten Siliciumbereichen
DE4213244C2 (de) Halbleitereinrichtung und Verfahren zu deren Herstellung
DE4445345C2 (de) Verfahren zur Herstellung eines Bipolartransistors
EP1166350B1 (de) Verfahren zur herstellung einer dram-struktur mit vergrabenen bitleitungen oder grabenkondensatoren
DE2808257A1 (de) Halbleitervorrichtung und verfahren zu ihrer herstellung
DE4433086A1 (de) Halbleitervorrichtung und Verfahren zu deren Herstellung
DE2626739A1 (de) Verfahren zur herstellung von monolithisch integrierten halbleiterschaltungen mit durch ionenbombardement hervorgerufenen dielektrischen isolationszonen
EP0182088B1 (de) Schottky-Kontakt auf einer Halbleiteroberfläche und Verfahren zu dessen Herstellung
DE2539073B2 (de) Feldeffekt-Transistor mit isolierter Gate-Elektrode und Verfahren zu dessen Herstellung
EP0025854A1 (de) Verfahren zum Herstellen von bipolaren Transistoren
DE4444776C2 (de) Verfahren zur Herstellung eines Bipolartransistors mit einer selbstjustierenden vertikalen Struktur
EP0029900B1 (de) Als bipolarer Transistor in einem Halbleitersubstrat ausgebildetes selbstjustiertes Schaltungs- oder Bauelement und Verfahren zur Herstellung
DE3825701A1 (de) Verfahren zur herstellung eines bipolaren transistors
DE2546314A1 (de) Feldeffekt-transistorstruktur und verfahren zur herstellung
DE19853268C2 (de) Feldeffektgesteuerter Transistor und Verfahren zu dessen Herstellung
DE4138063C2 (de) Halbleitereinrichtung und Verfahren zur Herstellung derselben
DE19650493A1 (de) Superselbstausgerichteter Bipolartransistor und Verfahren zu dessen Herstellung
DE2729973A1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE4138057C2 (de) Halbleitereinrichtung und Verfahren zu deren Herstellung
DE19717880C2 (de) Verfahren zur Bildung eines Isolationsbereichs einer Halbleitereinrichtung
DE19958062A1 (de) Verfahren zur Herstellung eines Bipolartransistors und Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit einem solchen Bipolartransistor
DE69033593T2 (de) Verfahren zur Herstellung einer integrierten Halbleiterschaltung mit einer Isolationszone
DE2758283C2 (de) Verfahren zur Herstellung voneinander isolierter Halbleiterschaltungen

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee