DE3888927T2 - Taktwiedergewinnungsanordnung. - Google Patents
Taktwiedergewinnungsanordnung.Info
- Publication number
- DE3888927T2 DE3888927T2 DE3888927T DE3888927T DE3888927T2 DE 3888927 T2 DE3888927 T2 DE 3888927T2 DE 3888927 T DE3888927 T DE 3888927T DE 3888927 T DE3888927 T DE 3888927T DE 3888927 T2 DE3888927 T2 DE 3888927T2
- Authority
- DE
- Germany
- Prior art keywords
- clock recovery
- recovery arrangement
- arrangement
- clock
- recovery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000011084 recovery Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
- H03D3/24—Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Power Engineering (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/123,040 US4821297A (en) | 1987-11-19 | 1987-11-19 | Digital phase locked loop clock recovery scheme |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3888927D1 DE3888927D1 (de) | 1994-05-11 |
DE3888927T2 true DE3888927T2 (de) | 1994-10-20 |
Family
ID=22406386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3888927T Expired - Fee Related DE3888927T2 (de) | 1987-11-19 | 1988-11-09 | Taktwiedergewinnungsanordnung. |
Country Status (7)
Country | Link |
---|---|
US (1) | US4821297A (de) |
EP (1) | EP0317159B1 (de) |
JP (1) | JPH01161936A (de) |
KR (1) | KR910007714B1 (de) |
CA (1) | CA1288839C (de) |
DE (1) | DE3888927T2 (de) |
ES (1) | ES2050710T3 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6891906B1 (en) | 1997-09-12 | 2005-05-10 | Mitsubishi Denki Kabushiki Kaisha | Demodulator, clock recovery circuit, demodulation method and clock recovery method |
DE102004016359A1 (de) * | 2004-04-02 | 2005-10-27 | Texas Instruments Deutschland Gmbh | Abtastverfahren und -vorrichtung |
Families Citing this family (83)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1301260C (en) * | 1988-01-21 | 1992-05-19 | Norio Yoshida | Synchronizer for establishing synchronization between data and clock signals |
EP0389696A1 (de) * | 1989-03-29 | 1990-10-03 | International Business Machines Corporation | Empfänger für serielle Daten |
JPH02260936A (ja) * | 1989-03-31 | 1990-10-23 | Toshiba Corp | クロック抽出回路 |
JPH0369238A (ja) * | 1989-08-08 | 1991-03-25 | Mitsubishi Electric Corp | 復調データ識別判定装置 |
US5172395A (en) * | 1989-08-22 | 1992-12-15 | Cincinnati Electronics Corporation | Method of and apparatus for deriving an indication of noise content of data bits |
US5140620A (en) * | 1989-09-20 | 1992-08-18 | Data Broadcasting Corporation | Method and apparatus for recovering data, such as teletext data encoded into television signals |
CA2001266C (en) * | 1989-10-23 | 1996-08-06 | John Robert Long | Digital phase aligner and method for its operation |
GB8924202D0 (en) * | 1989-10-27 | 1989-12-13 | Ncr Co | Digital phase lock loop decoder |
US5103464A (en) * | 1990-05-31 | 1992-04-07 | Northern Telecom Limited | Method and apparatus for timing recovery in digital data communications systems |
EP0470505B1 (de) * | 1990-08-08 | 1997-01-02 | National Semiconductor Corporation | Synchrone Detektion von FSK-Signalen |
US5182749A (en) * | 1990-12-21 | 1993-01-26 | Motorola, Inc. | Receiver for recovering data in a forward and reverse direction in time |
US5148113A (en) * | 1990-11-29 | 1992-09-15 | Northern Telecom Ltd. | Clock phase alignment |
US5109394A (en) * | 1990-12-24 | 1992-04-28 | Ncr Corporation | All digital phase locked loop |
EP0502260B1 (de) * | 1991-03-05 | 1996-06-12 | ALCATEL BELL Naamloze Vennootschap | Synchronisierschaltung |
US5287359A (en) * | 1991-04-08 | 1994-02-15 | Digital Equipment Corporation | Synchronous decoder for self-clocking signals |
US5259005A (en) * | 1992-03-26 | 1993-11-02 | Motorola, Inc. | Apparatus for and method of synchronizing a clock signal |
US5255292A (en) * | 1992-03-27 | 1993-10-19 | Motorola, Inc. | Method and apparatus for modifying a decision-directed clock recovery system |
SE515076C2 (sv) * | 1992-07-01 | 2001-06-05 | Ericsson Telefon Ab L M | Multiplexor-/demultiplexorkrets |
US5491729A (en) * | 1992-07-06 | 1996-02-13 | 3Com Corporation | Digital phase-locked data recovery circuit |
US5473638A (en) * | 1993-01-06 | 1995-12-05 | Glenayre Electronics, Inc. | Digital signal processor delay equalization for use in a paging system |
US5400370A (en) * | 1993-02-24 | 1995-03-21 | Advanced Micro Devices Inc. | All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging |
FR2705850B1 (fr) * | 1993-05-25 | 1995-06-30 | Cit Alcatel | Dispositif de rephasage d'un signal numérique transmis suivant une transmission synchrone et susceptible d'être affecté de gigue. |
FI106824B (fi) * | 1993-07-05 | 2001-04-12 | Nokia Networks Oy | Tukiasema |
US5561692A (en) * | 1993-12-09 | 1996-10-01 | Northern Telecom Limited | Clock phase shifting method and apparatus |
US5469466A (en) * | 1994-01-18 | 1995-11-21 | Hewlett-Packard Company | System for highly repeatable clock parameter recovery from data modulated signals |
GB9403724D0 (en) * | 1994-02-25 | 1994-04-13 | Texas Instruments Ltd | A method and apparatus for receiving a data signal and a digital filter circuit |
KR970002949B1 (ko) * | 1994-05-25 | 1997-03-13 | 삼성전자 주식회사 | 디지탈 통신시스템의 클럭발생방법 및 그 회로 |
US5541961A (en) * | 1994-08-15 | 1996-07-30 | At&T Corp. | Digitally controlled high resolution hybrid phase synthesizer |
US5539784A (en) * | 1994-09-30 | 1996-07-23 | At&T Corp. | Refined timing recovery circuit |
TW255079B (en) * | 1994-09-30 | 1995-08-21 | At & T Corp | Communications unit with data and clock recovery circuit |
US5541759A (en) * | 1995-05-09 | 1996-07-30 | Microsym Computers, Inc. | Single fiber transceiver and network |
US5608357A (en) * | 1995-09-12 | 1997-03-04 | Vlsi Technology, Inc. | High speed phase aligner with jitter removal |
US5920600A (en) * | 1995-09-18 | 1999-07-06 | Oki Electric Industry Co., Ltd. | Bit phase synchronizing circuitry for controlling phase and frequency, and PLL circuit therefor |
US5699389A (en) * | 1995-09-28 | 1997-12-16 | Motorola, Inc. | Oversampling correlator with virtual clock phase for a telecommunications device |
US5663991A (en) * | 1996-03-08 | 1997-09-02 | International Business Machines Corporation | Integrated circuit chip having built-in self measurement for PLL jitter and phase error |
US5870446A (en) * | 1996-03-11 | 1999-02-09 | Adtran, Inc. | Mechanism for automatically adjusting the phase of a transmission strobe clock signal to correct for misalignment of transmission clock and data signals |
JPH10260663A (ja) * | 1997-01-14 | 1998-09-29 | Toshiba Corp | ジッタ補正回路および平面表示装置 |
US5982834A (en) * | 1997-05-09 | 1999-11-09 | Sun Microsystems, Incorporated | Clock recovery system for high speed small amplitude data stream |
JPH10336024A (ja) * | 1997-05-30 | 1998-12-18 | Nec Ic Microcomput Syst Ltd | 位相差検出装置及びこれを備える半導体装置 |
US5938780A (en) * | 1997-09-19 | 1999-08-17 | Teradyne, Inc. | Method for capturing digital data in an automatic test system |
JP3993297B2 (ja) * | 1998-04-01 | 2007-10-17 | 三菱電機株式会社 | 制御回路 |
US6629250B2 (en) * | 1999-04-23 | 2003-09-30 | Cray Inc. | Adjustable data delay using programmable clock shift |
US6262611B1 (en) * | 1999-06-24 | 2001-07-17 | Nec Corporation | High-speed data receiving circuit and method |
US6424684B1 (en) * | 1999-08-30 | 2002-07-23 | Micron Technology, Inc. | Method and apparatus for receiving synchronous data |
US6272193B1 (en) * | 1999-09-27 | 2001-08-07 | Genesis Microchip Corp. | Receiver to recover data encoded in a serial communication channel |
EP1091519A1 (de) * | 1999-10-05 | 2001-04-11 | Lucent Technologies Inc. | Takt- und Datenrückgewinnungsvorrichtung |
JP2001168848A (ja) * | 1999-12-07 | 2001-06-22 | Mitsubishi Electric Corp | デジタル同期回路 |
US20020085656A1 (en) * | 2000-08-30 | 2002-07-04 | Lee Sang-Hyun | Data recovery using data eye tracking |
US7642566B2 (en) * | 2006-06-12 | 2010-01-05 | Dsm Solutions, Inc. | Scalable process and structure of JFET for small and decreasing line widths |
AU2002213444A1 (en) * | 2000-10-06 | 2002-04-15 | Flextronics Semiconductor Design, Inc. | Coherent expandable high speed interface |
US6693985B2 (en) * | 2000-10-27 | 2004-02-17 | Silicon Image | Clock and data recovery method and apparatus |
EP1334411B1 (de) * | 2000-11-16 | 2014-09-10 | Invensys Systems, Inc. | Vorrichtung, steuersystem und verfahren zur induktiven kommunikation über eine isolationsbarriere |
GB2397675B (en) * | 2000-12-06 | 2004-09-29 | Fujitsu Ltd | Verification circuitry |
US7263646B2 (en) * | 2000-12-29 | 2007-08-28 | Intel Corporation | Method and apparatus for skew compensation |
US6552619B2 (en) | 2001-02-05 | 2003-04-22 | Pmc Sierra, Inc. | Multi-channel clock recovery circuit |
US7116744B2 (en) | 2001-03-29 | 2006-10-03 | Fujitsu Limited | Clock recovery circuit and receiver circuit for improving the error rate of signal reproduction |
US7167533B2 (en) * | 2001-06-30 | 2007-01-23 | Intel Corporation | Apparatus and method for communication link receiver having adaptive clock phase shifting |
US6462521B1 (en) * | 2001-07-17 | 2002-10-08 | Semtech Corporation | High-speed charge-mode controller for a multi-phase switched-mode power converter |
JP3817550B2 (ja) * | 2001-07-27 | 2006-09-06 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 外部early/late入力端子を有するクロック・データ・リカバリ・システム |
US7136443B2 (en) | 2001-10-26 | 2006-11-14 | International Business Machines Corporation | Sample selection and data alignment circuit |
EP1438802B8 (de) * | 2001-10-26 | 2008-09-24 | International Business Machines Corporation | Speicherschaltung und schaltung zur erkennung eines gültigen überganges |
GB2385753B (en) | 2002-02-22 | 2005-04-06 | Zarlink Semiconductor Ltd | A data processing circuit |
US7151813B2 (en) * | 2002-07-17 | 2006-12-19 | Intel Corporation | Techniques to reduce transmitted jitter |
DE10251950A1 (de) * | 2002-11-08 | 2004-05-19 | Hochschule Bremen | Schaltungsanordnung und Verfahren für Hochgeschwindigkeitsdatentransfer |
US7231008B2 (en) * | 2002-11-15 | 2007-06-12 | Vitesse Semiconductor Corporation | Fast locking clock and data recovery unit |
US7233636B2 (en) | 2003-03-14 | 2007-06-19 | Thomson Licensing | Technique for oversampling to reduce jitter |
US7221727B2 (en) * | 2003-04-01 | 2007-05-22 | Kingston Technology Corp. | All-digital phase modulator/demodulator using multi-phase clocks and digital PLL |
ATE498257T1 (de) | 2003-04-29 | 2011-02-15 | Ericsson Telefon Ab L M | Mehrphasentaktwiedergewinnung |
JP3990319B2 (ja) | 2003-06-09 | 2007-10-10 | 株式会社アドバンテスト | 伝送システム、受信装置、試験装置、及びテストヘッド |
US7940877B1 (en) * | 2003-11-26 | 2011-05-10 | Altera Corporation | Signal edge detection circuitry and methods |
US7453968B2 (en) | 2004-05-18 | 2008-11-18 | Altera Corporation | Dynamic phase alignment methods and apparatus |
US20060193417A1 (en) * | 2005-02-25 | 2006-08-31 | Tellabs Operations, Inc. | Systems and methods for switching between redundant clock signals |
US7681063B2 (en) * | 2005-03-30 | 2010-03-16 | Infineon Technologies Ag | Clock data recovery circuit with circuit loop disablement |
US7929866B2 (en) * | 2005-11-28 | 2011-04-19 | Alcatel Lucent | Passive optical network media access controller assisted clock recovery |
DE102006020107B3 (de) * | 2006-04-29 | 2007-10-25 | Infineon Technologies Ag | Datenempfänger mit Taktrückgewinnungsschaltung |
US7831004B2 (en) * | 2006-06-13 | 2010-11-09 | Panasonic Corporation | Synchronous detecting circuit |
TWI329873B (en) * | 2007-02-15 | 2010-09-01 | Realtek Semiconductor Corp | Sampling circuit and method |
JP4706885B2 (ja) * | 2007-03-30 | 2011-06-22 | 日本電気株式会社 | クロック・データ再生回路およびその制御方法 |
WO2011016141A1 (ja) * | 2009-08-04 | 2011-02-10 | 日本電気株式会社 | 周波数再生回路 |
WO2011016142A1 (ja) * | 2009-08-04 | 2011-02-10 | 日本電気株式会社 | クロック再生回路 |
US8798217B2 (en) * | 2010-11-03 | 2014-08-05 | Qualcomm Incorporated | Method and digital circuit for recovering a clock and data from an input signal using a digital frequency detection |
US8483344B2 (en) | 2011-06-13 | 2013-07-09 | Stephen C. Dillinger | Fast lock serializer-deserializer (SERDES) architecture |
TWI635706B (zh) | 2017-01-04 | 2018-09-11 | 晨星半導體股份有限公司 | 決定出取樣時脈訊號的取樣相位的方法及相關的電子裝置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3983498A (en) * | 1975-11-13 | 1976-09-28 | Motorola, Inc. | Digital phase lock loop |
US4012598A (en) * | 1976-01-14 | 1977-03-15 | Bell Telephone Laboratories, Incorporated | Method and means for pulse receiver synchronization |
US4218771A (en) * | 1978-12-04 | 1980-08-19 | Rockwell International Corporation | Automatic clock positioning circuit for a digital data transmission system |
US4357707A (en) * | 1979-04-11 | 1982-11-02 | Pertec Computer Corporation | Digital phase lock loop for flexible disk data recovery system |
JPS5619263A (en) * | 1979-07-26 | 1981-02-23 | Meidensha Electric Mfg Co Ltd | Waveform shaping circuit |
US4280099A (en) * | 1979-11-09 | 1981-07-21 | Sperry Corporation | Digital timing recovery system |
US4415984A (en) * | 1980-06-25 | 1983-11-15 | Burroughs Corporation | Synchronous clock regenerator for binary serial data signals |
US4363002A (en) * | 1980-11-13 | 1982-12-07 | Fuller Robert M | Clock recovery apparatus for phase shift keyed encoded data |
JPS58172081A (ja) * | 1982-04-02 | 1983-10-08 | Hitachi Ltd | 同期クロツク発生回路 |
JPS59143444A (ja) * | 1983-02-04 | 1984-08-17 | Hitachi Ltd | デイジタルフエ−ズロツクドル−プ回路 |
US4584695A (en) * | 1983-11-09 | 1986-04-22 | National Semiconductor Corporation | Digital PLL decoder |
JPH0614638B2 (ja) * | 1985-07-31 | 1994-02-23 | セルヴル ミシエル | 局部クロック信号と受信データ信号とを再同期させる機構 |
JPS62133836A (ja) * | 1985-12-06 | 1987-06-17 | Oki Electric Ind Co Ltd | クロツク再生装置 |
-
1987
- 1987-11-19 US US07/123,040 patent/US4821297A/en not_active Expired - Lifetime
-
1988
- 1988-11-09 EP EP88310520A patent/EP0317159B1/de not_active Expired - Lifetime
- 1988-11-09 DE DE3888927T patent/DE3888927T2/de not_active Expired - Fee Related
- 1988-11-09 ES ES88310520T patent/ES2050710T3/es not_active Expired - Lifetime
- 1988-11-16 CA CA000583286A patent/CA1288839C/en not_active Expired - Fee Related
- 1988-11-17 KR KR1019880015103A patent/KR910007714B1/ko not_active IP Right Cessation
- 1988-11-18 JP JP63290358A patent/JPH01161936A/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6891906B1 (en) | 1997-09-12 | 2005-05-10 | Mitsubishi Denki Kabushiki Kaisha | Demodulator, clock recovery circuit, demodulation method and clock recovery method |
DE102004016359A1 (de) * | 2004-04-02 | 2005-10-27 | Texas Instruments Deutschland Gmbh | Abtastverfahren und -vorrichtung |
Also Published As
Publication number | Publication date |
---|---|
ES2050710T3 (es) | 1994-06-01 |
EP0317159A3 (en) | 1990-09-05 |
KR910007714B1 (ko) | 1991-09-30 |
CA1288839C (en) | 1991-09-10 |
KR890009115A (ko) | 1989-07-15 |
US4821297A (en) | 1989-04-11 |
EP0317159A2 (de) | 1989-05-24 |
JPH01161936A (ja) | 1989-06-26 |
EP0317159B1 (de) | 1994-04-06 |
DE3888927D1 (de) | 1994-05-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN |
|
8339 | Ceased/non-payment of the annual fee |