DE69120244T2 - Synchronisierschaltung - Google Patents

Synchronisierschaltung

Info

Publication number
DE69120244T2
DE69120244T2 DE69120244T DE69120244T DE69120244T2 DE 69120244 T2 DE69120244 T2 DE 69120244T2 DE 69120244 T DE69120244 T DE 69120244T DE 69120244 T DE69120244 T DE 69120244T DE 69120244 T2 DE69120244 T2 DE 69120244T2
Authority
DE
Germany
Prior art keywords
synchronization circuit
synchronization
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69120244T
Other languages
English (en)
Other versions
DE69120244D1 (de
Inventor
Joannes Mathilda Jos Sevenhans
Jean-Jacques Schmit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Bell NV
Original Assignee
Alcatel Bell NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Bell NV filed Critical Alcatel Bell NV
Application granted granted Critical
Publication of DE69120244D1 publication Critical patent/DE69120244D1/de
Publication of DE69120244T2 publication Critical patent/DE69120244T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0016Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033Correction by delay
    • H04L7/0041Delay of data signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE69120244T 1991-03-05 1991-03-05 Synchronisierschaltung Expired - Fee Related DE69120244T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP91200475A EP0502260B1 (de) 1991-03-05 1991-03-05 Synchronisierschaltung

Publications (2)

Publication Number Publication Date
DE69120244D1 DE69120244D1 (de) 1996-07-18
DE69120244T2 true DE69120244T2 (de) 1997-01-23

Family

ID=8207535

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69120244T Expired - Fee Related DE69120244T2 (de) 1991-03-05 1991-03-05 Synchronisierschaltung

Country Status (4)

Country Link
US (1) US5341404A (de)
EP (1) EP0502260B1 (de)
CA (1) CA2062246A1 (de)
DE (1) DE69120244T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3212390B2 (ja) * 1992-11-17 2001-09-25 クラリオン株式会社 スライディング相関器
IL105180A (en) * 1993-03-28 1998-01-04 Israel State Fast frequency code
US5640430A (en) * 1993-09-02 1997-06-17 Motorola, Inc. Method for detecting valid data in a data stream
GB9403724D0 (en) * 1994-02-25 1994-04-13 Texas Instruments Ltd A method and apparatus for receiving a data signal and a digital filter circuit
JP3386221B2 (ja) * 1994-03-17 2003-03-17 富士通株式会社 非同期データのクロック乗換回路
DE4442506A1 (de) * 1994-11-30 1996-06-05 Sel Alcatel Ag Synchronisierungsüberachung in einem Netzwerk
KR100413765B1 (ko) * 2001-08-27 2003-12-31 삼성전자주식회사 비 정수배 오버 샘플링에 의해 전력 소모를 낮추는 데이터복원 회로
US7362837B2 (en) * 2003-08-29 2008-04-22 Intel Corporation Method and apparatus for clock deskew
US8798217B2 (en) * 2010-11-03 2014-08-05 Qualcomm Incorporated Method and digital circuit for recovering a clock and data from an input signal using a digital frequency detection
FR3094593B1 (fr) * 2019-03-29 2021-02-19 Teledyne E2V Semiconductors Sas Procédé de synchronisation de données numériques envoyées en série

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2377729A1 (fr) * 1977-01-14 1978-08-11 Thomson Csf Dispositif de decodage de signaux numeriques, et systeme comportant un tel dispositif
DE3441501A1 (de) * 1984-11-14 1986-05-15 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zum regenerieren und synchronisieren eines digitalen signals
US4821297A (en) * 1987-11-19 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Digital phase locked loop clock recovery scheme
EP0389696A1 (de) * 1989-03-29 1990-10-03 International Business Machines Corporation Empfänger für serielle Daten
US5073905A (en) * 1989-08-22 1991-12-17 Cincinnati Electronics Corporation Apparatus for and method of synchronizing a local oscillator to a received digital bit stream

Also Published As

Publication number Publication date
EP0502260A1 (de) 1992-09-09
CA2062246A1 (en) 1992-09-06
US5341404A (en) 1994-08-23
DE69120244D1 (de) 1996-07-18
EP0502260B1 (de) 1996-06-12

Similar Documents

Publication Publication Date Title
DE69119152T2 (de) Schaltungsanordnung
DE69213986T2 (de) Schaltungsanordnung
DE69206651T2 (de) Schaltungsanordnung
DE69332333D1 (de) Synchronisierungsschaltung
DE69216663T2 (de) Schaltkreis
DE69229668T2 (de) Synchrone Schaltung
DE59207307D1 (de) Synchronisierungseinrichtung
DE69119345T2 (de) Synchronisierungsschaltung
DE69207507T2 (de) Leiterplatte
DE69120244D1 (de) Synchronisierschaltung
DE69429583D1 (de) Synchronisierungsschaltungsanordnung
DE69220456T2 (de) Schaltungsanordnung
DE69531913D1 (de) Synchronisierungsschaltung
NO930097L (no) Synkroniserende delekrets
DE69114624D1 (de) Synchronisierungsschaltung.
DE69129676D1 (de) Synchronisierschaltung
DE69215149T2 (de) Vertikalsynchronisationsschaltung
KR920020384U (ko) 분주회로
DE69119363T2 (de) Halteschaltung
DE69320616T2 (de) Synchronisierungsschaltung
KR920015896U (ko) 위상동기회로
KR920015535U (ko) 바이호닉 회로
KR930003793U (ko) 대역가변 dpll회로
FI924266A (fi) Kopplingsanordning
KR940018178U (ko) 클럭 동기회로

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee