DE69207507T2 - Leiterplatte - Google Patents

Leiterplatte

Info

Publication number
DE69207507T2
DE69207507T2 DE69207507T DE69207507T DE69207507T2 DE 69207507 T2 DE69207507 T2 DE 69207507T2 DE 69207507 T DE69207507 T DE 69207507T DE 69207507 T DE69207507 T DE 69207507T DE 69207507 T2 DE69207507 T2 DE 69207507T2
Authority
DE
Germany
Prior art keywords
pcb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69207507T
Other languages
English (en)
Other versions
DE69207507D1 (de
Inventor
Keizo Harada
Takatoshi Takikawa
Takao Maeda
Shunsuke Ban
Shosaku Yamanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3030185A external-priority patent/JPH04268752A/ja
Priority claimed from JP3056556A external-priority patent/JPH04291747A/ja
Priority claimed from JP3056522A external-priority patent/JPH04291748A/ja
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Application granted granted Critical
Publication of DE69207507D1 publication Critical patent/DE69207507D1/de
Publication of DE69207507T2 publication Critical patent/DE69207507T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49531Additional leads the additional leads being a wiring board
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
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    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/0179Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0302Properties and characteristics in general
    • H05K2201/0317Thin film conductor layer; Thin film passive component
DE69207507T 1991-02-25 1992-02-24 Leiterplatte Expired - Fee Related DE69207507T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP3030185A JPH04268752A (ja) 1991-02-25 1991-02-25 配線基板
JP3056556A JPH04291747A (ja) 1991-03-20 1991-03-20 配線基板
JP3056522A JPH04291748A (ja) 1991-03-20 1991-03-20 配線基板
PCT/JP1992/000198 WO1992015117A1 (en) 1991-02-25 1992-02-24 Wiring board

Publications (2)

Publication Number Publication Date
DE69207507D1 DE69207507D1 (de) 1996-02-22
DE69207507T2 true DE69207507T2 (de) 1996-09-12

Family

ID=27286870

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69207507T Expired - Fee Related DE69207507T2 (de) 1991-02-25 1992-02-24 Leiterplatte

Country Status (5)

Country Link
US (1) US5369220A (de)
EP (1) EP0526656B1 (de)
CA (1) CA2080814C (de)
DE (1) DE69207507T2 (de)
WO (1) WO1992015117A1 (de)

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Publication number Priority date Publication date Assignee Title
DE69418037T2 (de) * 1994-08-02 1999-08-26 St Microelectronics Srl Leistungshalbleitervorrichtung aus MOS-Technology-Chips und Gehäuseaufbau
DE69605989T2 (de) * 1995-03-20 2000-08-17 Koninkl Philips Electronics Nv Glasversiegelte halbleiteranordnung bestehend aus einem halbleiterkörper, der mittels einer silber-aluminium-verbindungsschicht mit einer senke verbunden ist
JP3422144B2 (ja) * 1995-09-22 2003-06-30 ソニー株式会社 半導体パッケージの製造方法
US6144100A (en) * 1997-06-05 2000-11-07 Texas Instruments Incorporated Integrated circuit with bonding layer over active circuitry
USD419959S (en) * 1998-11-25 2000-02-01 Amoroso Eugene C Conductive ink traces pattern on a medium
JP4958898B2 (ja) * 2005-04-28 2012-06-20 セカンド サイト メディカル プロダクツ インコーポレイテッド 移植可能な神経刺激装置のパッケージ
EP2422841B1 (de) * 2006-08-18 2013-10-09 Second Sight Medical Products, Inc. Verpackung für eine implantierbare Nervenstimulationsvorrichtung
US8125060B2 (en) 2006-12-08 2012-02-28 Infineon Technologies Ag Electronic component with layered frame
EP1945012B1 (de) * 2007-01-10 2014-09-24 Tridonic Jennersdorf GmbH LED-Modul mit Goldkontaktierung
US9859219B1 (en) 2017-01-24 2018-01-02 International Business Machines Corporation Copper wiring structures with copper titanium encapsulation
TWI719241B (zh) * 2017-08-18 2021-02-21 景碩科技股份有限公司 可做電性測試的多層電路板及其製法
JP7154818B2 (ja) * 2018-05-10 2022-10-18 ローム株式会社 半導体装置および半導体装置の製造方法

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DE2554691C2 (de) * 1974-12-10 1982-11-18 Western Electric Co., Inc., 10038 New York, N.Y. Verfahren zum Herstellen elektrischer Leiter auf einem isolierenden Substrat und danach hergestellte Dünnschichtschaltung
US4016050A (en) * 1975-05-12 1977-04-05 Bell Telephone Laboratories, Incorporated Conduction system for thin film and hybrid integrated circuits
US4420364A (en) * 1976-11-02 1983-12-13 Sharp Kabushiki Kaisha High-insulation multi-layer device formed on a metal substrate
JPS6034257B2 (ja) * 1980-05-26 1985-08-07 京セラ株式会社 金の導電層を有する電子部品
JPS59167038A (ja) * 1983-03-14 1984-09-20 Hitachi Ltd 光半導体素子用サブマウントの構造
JPS60136294A (ja) * 1983-12-23 1985-07-19 株式会社日立製作所 セラミック多層配線回路板
FR2567709B1 (fr) * 1984-07-11 1990-11-09 Nec Corp Ensemble a paillette comprenant un substrat de cablage multi-couche
JPH0691177B2 (ja) * 1985-04-16 1994-11-14 富士通株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
CA2080814A1 (en) 1992-08-26
US5369220A (en) 1994-11-29
EP0526656A4 (en) 1993-04-14
WO1992015117A1 (en) 1992-09-03
DE69207507D1 (de) 1996-02-22
EP0526656A1 (de) 1993-02-10
EP0526656B1 (de) 1996-01-10
CA2080814C (en) 1997-11-25

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