DE69207507T2 - Leiterplatte - Google Patents
LeiterplatteInfo
- Publication number
- DE69207507T2 DE69207507T2 DE69207507T DE69207507T DE69207507T2 DE 69207507 T2 DE69207507 T2 DE 69207507T2 DE 69207507 T DE69207507 T DE 69207507T DE 69207507 T DE69207507 T DE 69207507T DE 69207507 T2 DE69207507 T2 DE 69207507T2
- Authority
- DE
- Germany
- Prior art keywords
- pcb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0317—Thin film conductor layer; Thin film passive component
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3030185A JPH04268752A (ja) | 1991-02-25 | 1991-02-25 | 配線基板 |
JP3056556A JPH04291747A (ja) | 1991-03-20 | 1991-03-20 | 配線基板 |
JP3056522A JPH04291748A (ja) | 1991-03-20 | 1991-03-20 | 配線基板 |
PCT/JP1992/000198 WO1992015117A1 (en) | 1991-02-25 | 1992-02-24 | Wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69207507D1 DE69207507D1 (de) | 1996-02-22 |
DE69207507T2 true DE69207507T2 (de) | 1996-09-12 |
Family
ID=27286870
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69207507T Expired - Fee Related DE69207507T2 (de) | 1991-02-25 | 1992-02-24 | Leiterplatte |
Country Status (5)
Country | Link |
---|---|
US (1) | US5369220A (de) |
EP (1) | EP0526656B1 (de) |
CA (1) | CA2080814C (de) |
DE (1) | DE69207507T2 (de) |
WO (1) | WO1992015117A1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69418037T2 (de) * | 1994-08-02 | 1999-08-26 | St Microelectronics Srl | Leistungshalbleitervorrichtung aus MOS-Technology-Chips und Gehäuseaufbau |
DE69605989T2 (de) * | 1995-03-20 | 2000-08-17 | Koninkl Philips Electronics Nv | Glasversiegelte halbleiteranordnung bestehend aus einem halbleiterkörper, der mittels einer silber-aluminium-verbindungsschicht mit einer senke verbunden ist |
JP3422144B2 (ja) * | 1995-09-22 | 2003-06-30 | ソニー株式会社 | 半導体パッケージの製造方法 |
US6144100A (en) * | 1997-06-05 | 2000-11-07 | Texas Instruments Incorporated | Integrated circuit with bonding layer over active circuitry |
USD419959S (en) * | 1998-11-25 | 2000-02-01 | Amoroso Eugene C | Conductive ink traces pattern on a medium |
JP4958898B2 (ja) * | 2005-04-28 | 2012-06-20 | セカンド サイト メディカル プロダクツ インコーポレイテッド | 移植可能な神経刺激装置のパッケージ |
EP2422841B1 (de) * | 2006-08-18 | 2013-10-09 | Second Sight Medical Products, Inc. | Verpackung für eine implantierbare Nervenstimulationsvorrichtung |
US8125060B2 (en) | 2006-12-08 | 2012-02-28 | Infineon Technologies Ag | Electronic component with layered frame |
EP1945012B1 (de) * | 2007-01-10 | 2014-09-24 | Tridonic Jennersdorf GmbH | LED-Modul mit Goldkontaktierung |
US9859219B1 (en) | 2017-01-24 | 2018-01-02 | International Business Machines Corporation | Copper wiring structures with copper titanium encapsulation |
TWI719241B (zh) * | 2017-08-18 | 2021-02-21 | 景碩科技股份有限公司 | 可做電性測試的多層電路板及其製法 |
JP7154818B2 (ja) * | 2018-05-10 | 2022-10-18 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2554691C2 (de) * | 1974-12-10 | 1982-11-18 | Western Electric Co., Inc., 10038 New York, N.Y. | Verfahren zum Herstellen elektrischer Leiter auf einem isolierenden Substrat und danach hergestellte Dünnschichtschaltung |
US4016050A (en) * | 1975-05-12 | 1977-04-05 | Bell Telephone Laboratories, Incorporated | Conduction system for thin film and hybrid integrated circuits |
US4420364A (en) * | 1976-11-02 | 1983-12-13 | Sharp Kabushiki Kaisha | High-insulation multi-layer device formed on a metal substrate |
JPS6034257B2 (ja) * | 1980-05-26 | 1985-08-07 | 京セラ株式会社 | 金の導電層を有する電子部品 |
JPS59167038A (ja) * | 1983-03-14 | 1984-09-20 | Hitachi Ltd | 光半導体素子用サブマウントの構造 |
JPS60136294A (ja) * | 1983-12-23 | 1985-07-19 | 株式会社日立製作所 | セラミック多層配線回路板 |
FR2567709B1 (fr) * | 1984-07-11 | 1990-11-09 | Nec Corp | Ensemble a paillette comprenant un substrat de cablage multi-couche |
JPH0691177B2 (ja) * | 1985-04-16 | 1994-11-14 | 富士通株式会社 | 半導体装置の製造方法 |
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1992
- 1992-02-24 DE DE69207507T patent/DE69207507T2/de not_active Expired - Fee Related
- 1992-02-24 US US07/949,474 patent/US5369220A/en not_active Expired - Fee Related
- 1992-02-24 CA CA 2080814 patent/CA2080814C/en not_active Expired - Fee Related
- 1992-02-24 EP EP92905294A patent/EP0526656B1/de not_active Expired - Lifetime
- 1992-02-24 WO PCT/JP1992/000198 patent/WO1992015117A1/ja active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
CA2080814A1 (en) | 1992-08-26 |
US5369220A (en) | 1994-11-29 |
EP0526656A4 (en) | 1993-04-14 |
WO1992015117A1 (en) | 1992-09-03 |
DE69207507D1 (de) | 1996-02-22 |
EP0526656A1 (de) | 1993-02-10 |
EP0526656B1 (de) | 1996-01-10 |
CA2080814C (en) | 1997-11-25 |
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8339 | Ceased/non-payment of the annual fee |