KR920015896U - 위상동기회로 - Google Patents

위상동기회로

Info

Publication number
KR920015896U
KR920015896U KR2019910001360U KR910001360U KR920015896U KR 920015896 U KR920015896 U KR 920015896U KR 2019910001360 U KR2019910001360 U KR 2019910001360U KR 910001360 U KR910001360 U KR 910001360U KR 920015896 U KR920015896 U KR 920015896U
Authority
KR
South Korea
Prior art keywords
synchronization circuit
phase synchronization
phase
circuit
synchronization
Prior art date
Application number
KR2019910001360U
Other languages
English (en)
Other versions
KR930005441Y1 (ko
Inventor
마병인
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019910001360U priority Critical patent/KR930005441Y1/ko
Publication of KR920015896U publication Critical patent/KR920015896U/ko
Application granted granted Critical
Publication of KR930005441Y1 publication Critical patent/KR930005441Y1/ko

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
KR2019910001360U 1991-01-30 1991-01-30 위상동기회로 KR930005441Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019910001360U KR930005441Y1 (ko) 1991-01-30 1991-01-30 위상동기회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910001360U KR930005441Y1 (ko) 1991-01-30 1991-01-30 위상동기회로

Publications (2)

Publication Number Publication Date
KR920015896U true KR920015896U (ko) 1992-08-17
KR930005441Y1 KR930005441Y1 (ko) 1993-08-16

Family

ID=19310368

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019910001360U KR930005441Y1 (ko) 1991-01-30 1991-01-30 위상동기회로

Country Status (1)

Country Link
KR (1) KR930005441Y1 (ko)

Also Published As

Publication number Publication date
KR930005441Y1 (ko) 1993-08-16

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