ATE334523T1 - Speicherschaltung und schaltung zur erkennung eines gültigen überganges - Google Patents

Speicherschaltung und schaltung zur erkennung eines gültigen überganges

Info

Publication number
ATE334523T1
ATE334523T1 AT02783062T AT02783062T ATE334523T1 AT E334523 T1 ATE334523 T1 AT E334523T1 AT 02783062 T AT02783062 T AT 02783062T AT 02783062 T AT02783062 T AT 02783062T AT E334523 T1 ATE334523 T1 AT E334523T1
Authority
AT
Austria
Prior art keywords
circuit
transition
data
signal
over sampled
Prior art date
Application number
AT02783062T
Other languages
English (en)
Inventor
Philippe Hauviller
Vincent Vallet
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE334523T1 publication Critical patent/ATE334523T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/069—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection by detecting edges or zero crossings
AT02783062T 2001-10-26 2002-10-10 Speicherschaltung und schaltung zur erkennung eines gültigen überganges ATE334523T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01480101 2001-10-26

Publications (1)

Publication Number Publication Date
ATE334523T1 true ATE334523T1 (de) 2006-08-15

Family

ID=8183415

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02783062T ATE334523T1 (de) 2001-10-26 2002-10-10 Speicherschaltung und schaltung zur erkennung eines gültigen überganges

Country Status (7)

Country Link
EP (1) EP1438802B8 (de)
JP (1) JP3813151B2 (de)
KR (1) KR100634193B1 (de)
CN (1) CN100531026C (de)
AT (1) ATE334523T1 (de)
DE (1) DE60213443T2 (de)
WO (1) WO2003036853A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1316391C (zh) * 2003-08-28 2007-05-16 旺宏电子股份有限公司 超取样资料恢复装置及方法
JP4480536B2 (ja) * 2003-12-05 2010-06-16 株式会社リコー データリカバリ方法およびデータリカバリ回路
US7085668B2 (en) * 2004-08-20 2006-08-01 Teradyne, Inc. Time measurement method using quadrature sine waves
US7292665B2 (en) 2004-12-16 2007-11-06 Genesis Microchip Inc. Method and apparatus for reception of data over digital transmission link
CN100379193C (zh) * 2005-03-02 2008-04-02 威盛电子股份有限公司 在时钟数据再生系统中时钟的撷取方法和撷取电路
JP4676792B2 (ja) * 2005-03-17 2011-04-27 株式会社リコー データリカバリ方法、データリカバリ回路、データ送受信装置及び情報処理装置
US7801257B2 (en) * 2005-09-28 2010-09-21 Genesis Microchip Inc Adaptive reception techniques for over-sampled receivers
CN101354688B (zh) * 2007-07-27 2010-08-25 佛山市顺德区顺达电脑厂有限公司 数据传输速率调校装置及方法
CN101599926B (zh) * 2008-06-04 2012-11-21 联咏科技股份有限公司 差动传输器及其数据截取自动调整方法
US8605849B2 (en) * 2010-10-15 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Glitch free oversampling clock and data recovery
CN102510328B (zh) * 2011-12-29 2014-10-22 成都三零嘉微电子有限公司 一种高速并行接口电路
US9137008B2 (en) * 2013-07-23 2015-09-15 Qualcomm Incorporated Three phase clock recovery delay calibration
US20150146824A1 (en) * 2013-11-26 2015-05-28 Seagate Technology Llc Indexed i/o symbol communications
CN110489372A (zh) * 2019-07-22 2019-11-22 珠海泰芯半导体有限公司 滤波单元、时钟数据恢复电路及高速usb时钟数据恢复电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821297A (en) * 1987-11-19 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Digital phase locked loop clock recovery scheme
US6081561A (en) * 1994-02-25 2000-06-27 Texas Instruments Incorporated Method and apparatus for receiving and reconstituting a data signal employing oversampling and selection of a sampled data signal remote from transitions in the data signal
US5822386A (en) * 1995-11-29 1998-10-13 Lucent Technologies Inc. Phase recovery circuit for high speed and high density applications
US6307906B1 (en) * 1997-10-07 2001-10-23 Applied Micro Circuits Corporation Clock and data recovery scheme for multi-channel data communications receivers
US6285722B1 (en) * 1997-12-05 2001-09-04 Telcordia Technologies, Inc. Method and apparatus for variable bit rate clock recovery
JP3622685B2 (ja) * 2000-10-19 2005-02-23 セイコーエプソン株式会社 サンプリングクロック生成回路、データ転送制御装置及び電子機器

Also Published As

Publication number Publication date
KR20040045006A (ko) 2004-05-31
DE60213443D1 (de) 2006-09-07
KR100634193B1 (ko) 2006-10-16
CN100531026C (zh) 2009-08-19
EP1438802B8 (de) 2008-09-24
JP2005506798A (ja) 2005-03-03
WO2003036853A1 (en) 2003-05-01
CN1692597A (zh) 2005-11-02
DE60213443T2 (de) 2007-08-23
EP1438802B1 (de) 2006-07-26
JP3813151B2 (ja) 2006-08-23
EP1438802A1 (de) 2004-07-21

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