ATE329407T1 - Datenrückgewinnung mit nachführung des datenaugenmusters - Google Patents

Datenrückgewinnung mit nachführung des datenaugenmusters

Info

Publication number
ATE329407T1
ATE329407T1 AT01968304T AT01968304T ATE329407T1 AT E329407 T1 ATE329407 T1 AT E329407T1 AT 01968304 T AT01968304 T AT 01968304T AT 01968304 T AT01968304 T AT 01968304T AT E329407 T1 ATE329407 T1 AT E329407T1
Authority
AT
Austria
Prior art keywords
data
phase
clock
compare logic
input
Prior art date
Application number
AT01968304T
Other languages
English (en)
Inventor
Sang-Hyun Lee
Deog-Kyoon Jeong
Original Assignee
Silicon Image Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Image Inc filed Critical Silicon Image Inc
Application granted granted Critical
Publication of ATE329407T1 publication Critical patent/ATE329407T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Image Analysis (AREA)
  • Image Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AT01968304T 2000-08-30 2001-08-30 Datenrückgewinnung mit nachführung des datenaugenmusters ATE329407T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22936900P 2000-08-30 2000-08-30
US09/943,029 US20020085656A1 (en) 2000-08-30 2001-08-29 Data recovery using data eye tracking

Publications (1)

Publication Number Publication Date
ATE329407T1 true ATE329407T1 (de) 2006-06-15

Family

ID=26923234

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01968304T ATE329407T1 (de) 2000-08-30 2001-08-30 Datenrückgewinnung mit nachführung des datenaugenmusters

Country Status (9)

Country Link
US (2) US20020085656A1 (de)
EP (1) EP1314252B1 (de)
JP (1) JP2004507963A (de)
KR (1) KR100921110B1 (de)
AT (1) ATE329407T1 (de)
AU (1) AU2001288559A1 (de)
CA (1) CA2387722A1 (de)
DE (1) DE60120426T2 (de)
WO (1) WO2002019528A2 (de)

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3636657B2 (ja) * 2000-12-21 2005-04-06 Ｎｅｃエレクトロニクス株式会社 クロックアンドデータリカバリ回路とそのクロック制御方法
US7263646B2 (en) * 2000-12-29 2007-08-28 Intel Corporation Method and apparatus for skew compensation
GB2375274A (en) * 2001-03-27 2002-11-06 Acuid Corp Ltd Receiver with automatic skew compensation
US7167533B2 (en) * 2001-06-30 2007-01-23 Intel Corporation Apparatus and method for communication link receiver having adaptive clock phase shifting
US7190754B1 (en) * 2001-12-24 2007-03-13 Rambus Inc. Transceiver with selectable data rate
US7197101B2 (en) * 2002-01-02 2007-03-27 Intel Corporation Phase interpolator based clock recovering
AU2002257637A1 (en) * 2002-03-08 2003-09-22 Optillion Ab Device and method for recovering data
EP1504271B1 (de) * 2002-05-03 2006-11-22 Agilent Technologies Deutschland GmbH Jitter-spektrum-analyse
US7092471B2 (en) * 2002-05-22 2006-08-15 Lucent Technologies Inc. Digital phase synchronization circuit
DE60206150T2 (de) * 2002-07-12 2006-01-26 Alcatel Eingangsschaltung für einen Multiplexer mit einem DLL Phasendetektor
US7245682B2 (en) * 2002-09-30 2007-07-17 Intel Corporation Determining an optimal sampling clock
JP4196657B2 (ja) * 2002-11-29 2008-12-17 株式会社日立製作所 データ再生方法およびデジタル制御型クロックデータリカバリ回路
US7260145B2 (en) * 2002-12-19 2007-08-21 International Business Machines Corporation Method and systems for analyzing the quality of high-speed signals
US7443941B2 (en) * 2003-01-22 2008-10-28 Rambus Inc. Method and system for phase offset cancellation in systems using multi-phase clocks
US20040223567A1 (en) * 2003-05-09 2004-11-11 Ming-Kang Liu Clock recovery system
US20040223568A1 (en) * 2003-05-09 2004-11-11 Ming-Kang Liu Phase sampling determination system
US7627029B2 (en) 2003-05-20 2009-12-01 Rambus Inc. Margin test methods and circuits
US7408981B2 (en) * 2003-05-20 2008-08-05 Rambus Inc. Methods and circuits for performing margining tests in the presence of a decision feedback equalizer
US7336749B2 (en) * 2004-05-18 2008-02-26 Rambus Inc. Statistical margin test methods and circuits
US7590175B2 (en) 2003-05-20 2009-09-15 Rambus Inc. DFE margin test methods and circuits that decouple sample and feedback timing
US7049869B2 (en) 2003-09-02 2006-05-23 Gennum Corporation Adaptive lock position circuit
TWI226774B (en) * 2003-10-15 2005-01-11 Via Tech Inc Clock and data recovery circuit
US7782932B2 (en) * 2004-04-23 2010-08-24 Texas Instruments Incorporated Circuit and method for evaluating the performance of an adaptive decision feedback equalizer-based serializer deserializer and serdes incorporating the same
WO2005109733A1 (en) * 2004-05-06 2005-11-17 Igor Anatolievich Abrosimov Clock frequency reduction in communications receiver with coding
WO2005122460A1 (en) * 2004-06-04 2005-12-22 Opelcomm, Inc. Clock recovery system and phase sampling determination system
US7508893B1 (en) * 2004-06-04 2009-03-24 Integrated Device Technology, Inc. Integrated circuits and methods with statistics-based input data signal sample timing
US7516029B2 (en) * 2004-06-09 2009-04-07 Rambus, Inc. Communication channel calibration using feedback
US7529329B2 (en) * 2004-08-10 2009-05-05 Applied Micro Circuits Corporation Circuit for adaptive sampling edge position control and a method therefor
US7583459B1 (en) * 2004-11-18 2009-09-01 Marvell International Ltd. Method and apparatus for write precompensation in a magnetic recording system
TWI320992B (en) * 2004-11-29 2010-02-21 Via Tech Inc Clock data recovery circuit with phase decision circuit
US20060222123A1 (en) * 2005-03-31 2006-10-05 Mobin Mohammad S Method and apparatus for monitoring a data eye in a clock and data recovery system
US8467489B2 (en) * 2005-08-24 2013-06-18 Hewlett-Packard Development Company, L.P. Data clock recovery system and method employing delayed data clock phase shifting
KR100795724B1 (ko) * 2005-08-24 2008-01-17 삼성전자주식회사 아이 사이즈 측정 회로, 데이터 통신 시스템의 수신기 및아이 사이즈 측정 방법
US7400181B2 (en) * 2005-09-30 2008-07-15 Agere Systems Inc. Method and apparatus for delay line control using receive data
JP4886276B2 (ja) 2005-11-17 2012-02-29 ザインエレクトロニクス株式会社 クロックデータ復元装置
US7738605B2 (en) 2005-12-23 2010-06-15 Agere Systems Inc. Method and apparatus for adjusting receiver gain based on received signal envelope detection
DE112007000767B4 (de) * 2006-03-31 2010-06-24 Anritsu Corp., Atsugi-shi Datenentscheidungsvorrichtung und Fehlermessvorrichtung
US8553720B2 (en) 2006-04-19 2013-10-08 Marvell World Trade Ltd. Adaptive speed control for MAC-PHY interfaces
US7649933B2 (en) * 2006-04-28 2010-01-19 Agere Systems Inc. Method and apparatus for determining a position of an offset latch employed for decision-feedback equalization
US8861580B2 (en) * 2006-05-16 2014-10-14 Agere Systems Llc Method and apparatus for determining one or more channel compensation parameters based on data eye monitoring
US8126039B2 (en) * 2006-05-16 2012-02-28 Agere Systems Inc. Methods and apparatus for evaluating the eye margin of a communications device using a data eye monitor
US20070271052A1 (en) * 2006-05-16 2007-11-22 Abel Christopher J Method and apparatus for measuring duty cycle based on data eye monitor
KR100780952B1 (ko) * 2006-06-27 2007-12-03 삼성전자주식회사 디스큐 장치 및 방법, 그리고 이를 이용한 데이터 수신장치및 방법
US7782934B2 (en) * 2006-09-18 2010-08-24 Silicon Image, Inc. Parameter scanning for signal over-sampling
US7606302B2 (en) * 2006-09-29 2009-10-20 Agere Systems Inc. Method and apparatus for non-linear decision-feedback equalization in the presence of asymmetric channel
US7711043B2 (en) * 2006-09-29 2010-05-04 Agere Systems Inc. Method and apparatus for determining latch position for decision-feedback equalization using single-sided eye
JP4557947B2 (ja) 2006-10-11 2010-10-06 ザインエレクトロニクス株式会社 クロックデータ復元装置
JP4557948B2 (ja) 2006-10-12 2010-10-06 ザインエレクトロニクス株式会社 クロックデータ復元装置
TWI329873B (en) * 2007-02-15 2010-09-01 Realtek Semiconductor Corp Sampling circuit and method
US7650550B2 (en) * 2007-02-27 2010-01-19 Globalfoundries Inc. Over temperature detection apparatus and method thereof
US7693088B2 (en) * 2007-03-14 2010-04-06 Agere Systems Inc. Method and apparatus for data rate detection using a data eye monitor
US8243752B2 (en) * 2007-04-04 2012-08-14 Marvell World Trade Ltd. Long-reach ethernet for 1000BASE-T and 10GBASE-T
US8050371B2 (en) * 2007-04-27 2011-11-01 Freescale Semiconductor, Inc. Method and system for compensating for the effect of phase drift in a data sampling clock
JP2008294730A (ja) * 2007-05-24 2008-12-04 Sony Corp 信号処理装置および方法、並びにプログラム
US8902963B2 (en) * 2007-09-28 2014-12-02 Agere Systems Inc. Methods and apparatus for determining threshold of one or more DFE transition latches based on incoming data eye
US7916819B2 (en) * 2007-10-10 2011-03-29 Himax Technologies Limited Receiver system and method for automatic skew-tuning
US8107522B2 (en) * 2007-10-11 2012-01-31 Agere Systems, Inc. Methods and apparatus for determining receiver filter coefficients for a plurality of phases
US8432959B2 (en) * 2007-10-31 2013-04-30 Agere Systems Llc Method and apparatus for equalization using one or more qualifiers
JP4558028B2 (ja) 2007-11-06 2010-10-06 ザインエレクトロニクス株式会社 クロックデータ復元装置
US8208521B2 (en) * 2007-12-31 2012-06-26 Agere Systems Inc. Methods and apparatus for detecting a loss of lock condition in a clock and data recovery system
US8040984B2 (en) * 2007-12-31 2011-10-18 Agere System Inc. Methods and apparatus for improved jitter tolerance in an SFP limit amplified signal
US7765078B2 (en) * 2007-12-31 2010-07-27 Agere Systems Inc. Method and apparatus for digital VCDL startup
US7869544B2 (en) * 2008-01-03 2011-01-11 International Business Machines Corporation System for measuring an eyewidth of a data signal in an asynchronous system
JP5166924B2 (ja) * 2008-03-11 2013-03-21 株式会社日立製作所 信号再生回路
JP4315462B1 (ja) * 2008-04-23 2009-08-19 シリコンライブラリ株式会社 オーディオ参照クロックを生成可能な受信装置
US8015429B2 (en) 2008-06-30 2011-09-06 Intel Corporation Clock and data recovery (CDR) method and apparatus
US8261160B1 (en) * 2008-07-30 2012-09-04 Lattice Semiconductor Corporation Synchronization of serial data signals
EP2335374A4 (de) * 2008-10-02 2012-03-28 Zenko Technologies Inc Datenabtastschaltung und verfahren zur takt- und datenwiedergewinnung
US8347153B2 (en) * 2008-10-10 2013-01-01 Teledyne Lecroy, Inc. Protocol aware error ratio tester
US8793541B2 (en) 2008-10-10 2014-07-29 Teledyne Lecroy, Inc. Link equalization tester
KR100992004B1 (ko) * 2008-12-12 2010-11-04 주식회사 하이닉스반도체 반도체 메모리 장치의 도메인 크로싱 회로
US8559580B2 (en) * 2009-06-30 2013-10-15 Lsi Corporation Asynchronous calibration for eye diagram generation
US20120126854A1 (en) * 2009-08-04 2012-05-24 Nec Corporation Frequency regeneration circuit and frequency regeneration method
WO2011016142A1 (ja) * 2009-08-04 2011-02-10 日本電気株式会社 クロック再生回路
JP5161196B2 (ja) * 2009-12-04 2013-03-13 株式会社日立製作所 クロック異常検知システム
CN102088327B (zh) * 2009-12-07 2013-09-11 华为技术有限公司 时钟数据恢复电路、光接收机和无源光网络设备
KR101034379B1 (ko) 2010-04-30 2011-05-16 전자부품연구원 클록없이 동작하는 등화기를 이용한 데이터 복원장치
JP5471962B2 (ja) * 2010-08-13 2014-04-16 富士通セミコンダクター株式会社 クロックデータ再生回路およびクロックデータ再生方法
US8693593B2 (en) * 2010-12-30 2014-04-08 Lsi Corporation Methods and apparatus for automatic gain control using samples taken at desired sampling phase and target voltage level
US8649476B2 (en) * 2011-04-07 2014-02-11 Lsi Corporation Adjusting sampling phase in a baud-rate CDR using timing skew
US8571159B1 (en) * 2011-12-02 2013-10-29 Altera Corporation Apparatus and methods for high-speed interpolator-based clock and data recovery
US9265458B2 (en) 2012-12-04 2016-02-23 Sync-Think, Inc. Application of smooth pursuit cognitive testing paradigms to clinical drug development
US9385858B2 (en) * 2013-02-20 2016-07-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Timing phase estimation for clock and data recovery
US9380976B2 (en) 2013-03-11 2016-07-05 Sync-Think, Inc. Optical neuroinformatics
US8860467B2 (en) * 2013-03-15 2014-10-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Biased bang-bang phase detector for clock and data recovery
WO2019028740A1 (en) * 2017-08-10 2019-02-14 Photonic Technologies (Shanghai) Co., Ltd. CLOCK RECOVERY CIRCUIT AND DATA
KR102478782B1 (ko) 2018-05-18 2022-12-20 삼성전자주식회사 시그마 레벨들간의 차이를 계산하는 아이 오프닝 측정 회로, 그것을 포함하는 수신기, 그리고 아이 오프닝을 측정하기 위한 방법
KR102648186B1 (ko) * 2018-12-24 2024-03-18 에스케이하이닉스 주식회사 트래이닝 기능을 갖는 반도체 시스템
CN110113270B (zh) * 2019-04-11 2021-04-23 北京达佳互联信息技术有限公司 网络通信的抖动控制方法、装置、终端及存储介质
WO2020256165A1 (ko) * 2019-06-18 2020-12-24 엘지전자 주식회사 신호 수신 방법 및 신호 수신 멀티미디어 디바이스
US20240012442A1 (en) * 2022-07-07 2024-01-11 Global Unichip Corporation Interface device and signal transceiving method thereof
US11979163B2 (en) * 2022-10-03 2024-05-07 Western Digital Technologies, Inc. Oversampled phase lock loop in a read channel

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3633115A (en) * 1970-04-22 1972-01-04 Itt Digital voltage controlled oscillator producing an output clock which follows the phase variation of an input clock
US4218771A (en) * 1978-12-04 1980-08-19 Rockwell International Corporation Automatic clock positioning circuit for a digital data transmission system
JPS59171230A (ja) * 1983-03-17 1984-09-27 Mitsubishi Electric Corp 擬似誤り率測定回路
US4538283A (en) * 1983-07-26 1985-08-27 Rockwell International Corporation Adaptive equalizer suitable for use with fiber optics
US4584695A (en) * 1983-11-09 1986-04-22 National Semiconductor Corporation Digital PLL decoder
US4821297A (en) * 1987-11-19 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Digital phase locked loop clock recovery scheme
JPH02250535A (ja) * 1989-03-24 1990-10-08 Nippon Telegr & Teleph Corp <Ntt> ビット位相同期回路
US5432480A (en) * 1993-04-08 1995-07-11 Northern Telecom Limited Phase alignment methods and apparatus
JPH07221800A (ja) * 1994-02-02 1995-08-18 Nec Corp データ識別再生回路
US5554945A (en) * 1994-02-15 1996-09-10 Rambus, Inc. Voltage controlled phase shifter with unlimited range
US5481563A (en) * 1994-03-14 1996-01-02 Network Systems Corporation Jitter measurement using a statistically locked loop
US5455540A (en) * 1994-10-26 1995-10-03 Cypress Semiconductor Corp. Modified bang-bang phase detector with ternary output
US5870445A (en) * 1995-12-27 1999-02-09 Raytheon Company Frequency independent clock synchronizer
US5896391A (en) * 1996-12-19 1999-04-20 Northern Telecom Limited Forward error correction assisted receiver optimization

Also Published As

Publication number Publication date
EP1314252B1 (de) 2006-06-07
EP1314252A2 (de) 2003-05-28
US20020085656A1 (en) 2002-07-04
JP2004507963A (ja) 2004-03-11
WO2002019528A3 (en) 2002-09-19
CA2387722A1 (en) 2002-03-07
US7315598B2 (en) 2008-01-01
KR100921110B1 (ko) 2009-10-08
AU2001288559A1 (en) 2002-03-13
WO2002019528A2 (en) 2002-03-07
KR20020077342A (ko) 2002-10-11
DE60120426D1 (de) 2006-07-20
US20070002990A1 (en) 2007-01-04
DE60120426T2 (de) 2007-01-04

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