DE3886283D1 - Halbleiterbauelement mit Bereichen unterschiedlicher Störstellenkonzentration. - Google Patents

Halbleiterbauelement mit Bereichen unterschiedlicher Störstellenkonzentration.

Info

Publication number
DE3886283D1
DE3886283D1 DE88110709T DE3886283T DE3886283D1 DE 3886283 D1 DE3886283 D1 DE 3886283D1 DE 88110709 T DE88110709 T DE 88110709T DE 3886283 T DE3886283 T DE 3886283T DE 3886283 D1 DE3886283 D1 DE 3886283D1
Authority
DE
Germany
Prior art keywords
areas
impurity concentration
semiconductor component
different impurity
different
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88110709T
Other languages
English (en)
Other versions
DE3886283T2 (de
Inventor
Shizuo C O Patent Divis Sawada
Syuso C O Patent Divisio Fujii
Masaki Ogihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62172231A external-priority patent/JPH0752755B2/ja
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3886283D1 publication Critical patent/DE3886283D1/de
Publication of DE3886283T2 publication Critical patent/DE3886283T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
DE88110709T 1987-07-10 1988-07-05 Halbleiterbauelement mit Bereichen unterschiedlicher Störstellenkonzentration. Expired - Fee Related DE3886283T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62172231A JPH0752755B2 (ja) 1987-07-10 1987-07-10 半導体装置の製造方法
JP15653888 1988-06-24

Publications (2)

Publication Number Publication Date
DE3886283D1 true DE3886283D1 (de) 1994-01-27
DE3886283T2 DE3886283T2 (de) 1994-05-11

Family

ID=26484251

Family Applications (2)

Application Number Title Priority Date Filing Date
DE88110709T Expired - Fee Related DE3886283T2 (de) 1987-07-10 1988-07-05 Halbleiterbauelement mit Bereichen unterschiedlicher Störstellenkonzentration.
DE3855945T Expired - Fee Related DE3855945T2 (de) 1987-07-10 1988-07-05 Halbleiterbauelement mit Bereichen unterschiedlicher Störstellenkonzentration

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE3855945T Expired - Fee Related DE3855945T2 (de) 1987-07-10 1988-07-05 Halbleiterbauelement mit Bereichen unterschiedlicher Störstellenkonzentration

Country Status (3)

Country Link
US (1) US5079613A (de)
EP (2) EP0509565B1 (de)
DE (2) DE3886283T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5324982A (en) 1985-09-25 1994-06-28 Hitachi, Ltd. Semiconductor memory device having bipolar transistor and structure to avoid soft error
US6740958B2 (en) 1985-09-25 2004-05-25 Renesas Technology Corp. Semiconductor memory device
US5260226A (en) * 1987-07-10 1993-11-09 Kabushiki Kaisha Toshiba Semiconductor device having different impurity concentration wells
US5726475A (en) * 1987-07-10 1998-03-10 Kabushiki Kaisha Toshiba Semiconductor device having different impurity concentration wells
DE3900769A1 (de) * 1989-01-12 1990-08-09 Fraunhofer Ges Forschung Integrierte schaltung mit zumindest einem n-kanal-fet und zumindest einem p-kanal-fet
JP2754072B2 (ja) * 1990-02-07 1998-05-20 三菱電機株式会社 半導体装置の入力回路
JP2523409B2 (ja) * 1990-05-02 1996-08-07 三菱電機株式会社 半導体記憶装置およびその製造方法
JP2619119B2 (ja) * 1990-06-21 1997-06-11 株式会社東芝 半導体集積回路
DE4143521C2 (de) * 1990-06-28 1995-04-06 Mitsubishi Electric Corp Halbleiterspeichervorrichtung
KR950009893B1 (ko) * 1990-06-28 1995-09-01 미쓰비시 뎅끼 가부시끼가이샤 반도체기억장치
JPH0567753A (ja) * 1991-04-17 1993-03-19 Mitsubishi Electric Corp 二重構造ウエルを有する半導体装置およびその製造方法
DE4212822C2 (de) * 1991-04-17 1994-06-16 Mitsubishi Electric Corp Halbleitervorrichtung mit Wannen und Verfahren zum Herstellen einer solchen
KR930009132B1 (ko) * 1991-04-24 1993-09-23 삼성전자 주식회사 초고집적 반도체 메모리장치의 제조방법
JP3128262B2 (ja) * 1991-05-28 2001-01-29 株式会社東芝 半導体集積回路装置
KR950009815B1 (ko) * 1991-12-23 1995-08-28 삼성전자주식회사 트리플웰 구조를 가지는 고집적 반도체 메모리 장치
US5250829A (en) * 1992-01-09 1993-10-05 International Business Machines Corporation Double well substrate plate trench DRAM cell array
US5264716A (en) * 1992-01-09 1993-11-23 International Business Machines Corporation Diffused buried plate trench dram cell array
US5595925A (en) * 1994-04-29 1997-01-21 Texas Instruments Incorporated Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein
JP4037470B2 (ja) * 1994-06-28 2008-01-23 エルピーダメモリ株式会社 半導体装置
US5696721A (en) * 1995-05-05 1997-12-09 Texas Instruments Incorporated Dynamic random access memory having row decoder with level translator for driving a word line voltage above and below an operating supply voltage range
JP3400891B2 (ja) * 1995-05-29 2003-04-28 三菱電機株式会社 半導体記憶装置およびその製造方法
US5908310A (en) * 1995-12-27 1999-06-01 International Business Machines Corporation Method to form a buried implanted plate for DRAM trench storage capacitors
JPH1084045A (ja) * 1996-09-06 1998-03-31 Matsushita Electron Corp 半導体集積回路装置およびその製造方法
US6433392B1 (en) * 1998-04-08 2002-08-13 Texas Instruments Incorporated Electrostatic discharge device and method
US6589834B1 (en) 1998-10-06 2003-07-08 Alliance Semiconductor Corporation Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current
JP2000216277A (ja) * 1999-01-20 2000-08-04 Nec Corp 半導体装置及びその製造方法
US6214675B1 (en) * 1999-02-08 2001-04-10 Lucent Technologies Inc. Method for fabricating a merged integrated circuit device
JP2000277629A (ja) * 1999-03-23 2000-10-06 Nec Corp 半導体記憶装置及びその製造方法
US6917095B1 (en) 2000-05-30 2005-07-12 Altera Corporation Integrated radio frequency circuits
JP2003258120A (ja) * 2002-03-07 2003-09-12 Seiko Epson Corp 半導体装置の製造方法
US7176530B1 (en) 2004-03-17 2007-02-13 National Semiconductor Corporation Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor
JP4938262B2 (ja) * 2004-08-25 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7095094B2 (en) * 2004-09-29 2006-08-22 Agere Systems Inc. Multiple doping level bipolar junctions transistors and method for forming

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5472691A (en) * 1977-11-21 1979-06-11 Toshiba Corp Semiconductor device
US4413401A (en) * 1979-07-23 1983-11-08 National Semiconductor Corporation Method for making a semiconductor capacitor
JPS57192070A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor memory unit
JPS57210665A (en) * 1981-06-19 1982-12-24 Mitsubishi Electric Corp Semiconductor memory device
JPS587860A (ja) * 1981-07-06 1983-01-17 Hitachi Ltd 半導体記憶装置
JPS5848959A (ja) * 1981-09-18 1983-03-23 Toshiba Corp 半導体装置
GB2148589B (en) * 1983-10-18 1987-04-23 Standard Telephones Cables Ltd Improvements in intergrated circuits
JPS60206163A (ja) * 1984-03-30 1985-10-17 Toshiba Corp 半導体記憶装置
US4672410A (en) * 1984-07-12 1987-06-09 Nippon Telegraph & Telephone Semiconductor memory device with trench surrounding each memory cell
US4673962A (en) * 1985-03-21 1987-06-16 Texas Instruments Incorporated Vertical DRAM cell and method
JPH0793282B2 (ja) * 1985-04-15 1995-10-09 株式会社日立製作所 半導体装置の製造方法
US4918502A (en) * 1986-11-28 1990-04-17 Hitachi, Ltd. Semiconductor memory having trench capacitor formed with sheath electrode

Also Published As

Publication number Publication date
DE3886283T2 (de) 1994-05-11
US5079613A (en) 1992-01-07
EP0298421A3 (en) 1989-03-15
DE3855945D1 (de) 1997-07-24
EP0298421A2 (de) 1989-01-11
DE3855945T2 (de) 1997-11-13
EP0509565A2 (de) 1992-10-21
EP0509565A3 (en) 1993-04-14
EP0509565B1 (de) 1997-06-18
EP0298421B1 (de) 1993-12-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee