DE3872673T2 - Verfahren zum testen von zellen von elektrisch programmierbaren speichern und entsprechende integrierte schaltung. - Google Patents

Verfahren zum testen von zellen von elektrisch programmierbaren speichern und entsprechende integrierte schaltung.

Info

Publication number
DE3872673T2
DE3872673T2 DE8888402905T DE3872673T DE3872673T2 DE 3872673 T2 DE3872673 T2 DE 3872673T2 DE 8888402905 T DE8888402905 T DE 8888402905T DE 3872673 T DE3872673 T DE 3872673T DE 3872673 T2 DE3872673 T2 DE 3872673T2
Authority
DE
Germany
Prior art keywords
integrated circuit
electrically programmable
programmable storage
corresponding integrated
testing cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888402905T
Other languages
English (en)
Other versions
DE3872673D1 (de
Inventor
Jean Devin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of DE3872673D1 publication Critical patent/DE3872673D1/de
Application granted granted Critical
Publication of DE3872673T2 publication Critical patent/DE3872673T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current
DE8888402905T 1987-11-24 1988-11-18 Verfahren zum testen von zellen von elektrisch programmierbaren speichern und entsprechende integrierte schaltung. Expired - Fee Related DE3872673T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8716236A FR2623653B1 (fr) 1987-11-24 1987-11-24 Procede de test de cellules de memoire electriquement programmable et circuit integre correspondant

Publications (2)

Publication Number Publication Date
DE3872673D1 DE3872673D1 (de) 1992-08-13
DE3872673T2 true DE3872673T2 (de) 1992-12-03

Family

ID=9357084

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888402905T Expired - Fee Related DE3872673T2 (de) 1987-11-24 1988-11-18 Verfahren zum testen von zellen von elektrisch programmierbaren speichern und entsprechende integrierte schaltung.

Country Status (6)

Country Link
US (1) US4958324A (de)
EP (1) EP0318363B1 (de)
JP (1) JP2928794B2 (de)
KR (1) KR890008851A (de)
DE (1) DE3872673T2 (de)
FR (1) FR2623653B1 (de)

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FR2629248B1 (fr) * 1988-03-25 1992-04-24 Sgs Thomson Microelectronics Procede de test de memoire a programmation unique et memoire correspondante
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US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
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US5195099A (en) * 1989-04-11 1993-03-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having improved error correcting circuit
US5353243A (en) 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
US5369593A (en) 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
FR2663774B1 (fr) * 1990-06-21 1992-09-25 Sgs Thomson Microelectronics Circuit de test de cellules memoires electriquement programmables.
US5528600A (en) * 1991-01-28 1996-06-18 Actel Corporation Testability circuits for logic arrays
JP3282188B2 (ja) * 1991-06-27 2002-05-13 日本電気株式会社 半導体メモリ装置
FR2683664A1 (fr) * 1991-11-13 1993-05-14 Sgs Thomson Microelectronics Memoire integree electriquement programmable a un seuil transistor.
US5235549A (en) * 1991-12-23 1993-08-10 Intel Corporation Semiconductor device with apparatus for performing electrical tests on single memory cells
US5255230A (en) * 1991-12-31 1993-10-19 Intel Corporation Method and apparatus for testing the continuity of static random access memory cells
JPH0612900A (ja) * 1992-06-29 1994-01-21 Mitsubishi Electric Corp 不揮発性半導体記憶装置
DE69326329T2 (de) * 1993-06-28 2000-04-13 St Microelectronics Srl Speicherzellen-Stromleseverfahren in Mikrosteuergerät
JPH0757472A (ja) * 1993-08-13 1995-03-03 Nec Corp 半導体集積回路装置
FR2714202B1 (fr) * 1993-12-22 1996-01-12 Sgs Thomson Microelectronics Mémoire en circuit intégré à temps de lecture amélioré.
US5680583A (en) 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
JPH08167296A (ja) * 1994-12-08 1996-06-25 Nippon Motorola Ltd 半導体記憶装置
US5559745A (en) * 1995-09-15 1996-09-24 Intel Corporation Static random access memory SRAM having weak write test circuit
US5870407A (en) * 1996-05-24 1999-02-09 Advanced Micro Devices, Inc. Method of screening memory cells at room temperature that would be rejected during hot temperature programming tests
US5930185A (en) * 1997-09-26 1999-07-27 Advanced Micro Devices, Inc. Data retention test for static memory cell
US5936892A (en) * 1996-09-30 1999-08-10 Advanced Micro Devices, Inc. Memory cell DC characterization apparatus and method
US5920517A (en) * 1996-09-30 1999-07-06 Advanced Micro Devices, Inc. Memory array test and characterization using isolated memory cell power supply
US5923601A (en) * 1996-09-30 1999-07-13 Advanced Micro Devices, Inc. Memory array sense amplifier test and characterization
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
FR2758645B1 (fr) * 1997-01-22 2001-12-14 Sgs Thomson Microelectronics Dispositif et procede de programmation d'une memoire
US5909049A (en) * 1997-02-11 1999-06-01 Actel Corporation Antifuse programmed PROM cell
US5960191A (en) 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6256241B1 (en) 2000-03-30 2001-07-03 Intel Corporation Short write test mode for testing static memory cells
KR100542695B1 (ko) * 2003-11-13 2006-01-11 주식회사 하이닉스반도체 반도체 소자의 테스트 모드 회로
JP4848126B2 (ja) * 2004-11-04 2011-12-28 オンセミコンダクター・トレーディング・リミテッド マイクロコンピュータ、マイクロコンピュータにおける不揮発性メモリのデータ保護方法
US7555424B2 (en) 2006-03-16 2009-06-30 Quickturn Design Systems, Inc. Method and apparatus for rewinding emulated memory circuits
US7388796B2 (en) * 2006-06-29 2008-06-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method for testing memory under worse-than-normal conditions

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US4228528B2 (en) * 1979-02-09 1992-10-06 Memory with redundant rows and columns
US4253059A (en) * 1979-05-14 1981-02-24 Fairchild Camera & Instrument Corp. EPROM Reliability test circuit
JPS5928560Y2 (ja) * 1979-11-13 1984-08-17 富士通株式会社 冗長ビットを有する記憶装置
JPS6035760B2 (ja) * 1980-12-18 1985-08-16 富士通株式会社 半導体記憶装置
JPS5853775A (ja) * 1981-09-26 1983-03-30 Fujitsu Ltd Ｉｃメモリ試験方法
US4519076A (en) * 1981-12-28 1985-05-21 National Semiconductor Corporation Memory core testing system
JPS5922295A (ja) * 1982-06-30 1984-02-04 Fujitsu Ltd 半導体記憶装置
US4502140A (en) * 1983-07-25 1985-02-26 Mostek Corporation GO/NO GO margin test circuit for semiconductor memory
US4609998A (en) * 1983-12-15 1986-09-02 Monolithic Memories, Inc. High conductance circuit for programmable integrated circuit
JPS60201598A (ja) * 1984-03-23 1985-10-12 Fujitsu Ltd 半導体集積回路
US4670878A (en) * 1984-08-14 1987-06-02 Texas Instruments Incorporated Column shift circuitry for high speed testing of semiconductor memory devices
JPS61178795A (ja) * 1985-02-01 1986-08-11 Toshiba Corp ダイナミツク型半導体記憶装置
US4720817A (en) * 1985-02-26 1988-01-19 Texas Instruments Incorporated Fuse selection of predecoder output
JPS61292755A (ja) * 1985-06-20 1986-12-23 Fujitsu Ltd 半導体集積回路
EP0214508B1 (de) * 1985-09-11 1991-09-25 Siemens Aktiengesellschaft Integrierter Halbleiterspeicher
US4734885A (en) * 1985-10-17 1988-03-29 Harris Corporation Programming arrangement for programmable devices
JPS62114200A (ja) * 1985-11-13 1987-05-25 Mitsubishi Electric Corp 半導体メモリ装置
JPS62121979A (ja) * 1985-11-22 1987-06-03 Mitsubishi Electric Corp 集積回路メモリ
IT1186430B (it) * 1985-12-12 1987-11-26 Sgs Microelettrica Spa Rpocedimento per la realizzazione di memorie a sola lettura in tecnologia nmos programmate mediante impiantazione ionica e memoria a sola lettura ottenuta mediante tale procedimento
JP2513462B2 (ja) * 1986-03-26 1996-07-03 株式会社日立製作所 マイクロ・コンピユ−タ
US4714839A (en) * 1986-03-27 1987-12-22 Advanced Micro Devices, Inc. Control circuit for disabling or enabling the provision of redundancy
US4731760A (en) * 1986-05-05 1988-03-15 Motorola, Inc. On-chip test circuitry for an ECL PROM
JPS63155494A (ja) * 1986-12-19 1988-06-28 Fujitsu Ltd 擬似スタテイツクメモリ装置

Also Published As

Publication number Publication date
JPH01171200A (ja) 1989-07-06
US4958324A (en) 1990-09-18
FR2623653A1 (fr) 1989-05-26
DE3872673D1 (de) 1992-08-13
KR890008851A (ko) 1989-07-12
JP2928794B2 (ja) 1999-08-03
EP0318363A1 (de) 1989-05-31
FR2623653B1 (fr) 1992-10-23
EP0318363B1 (de) 1992-07-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee